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orca ? series 2 field-programmable gate arrays data sheet june 1999 features n high-performance, cost-effective, low-power 0.35 m cmos technology (or2cxxa), 0.3 m cmos technology (or2txxa), and 0.25 m cmos technology (or2txxb), (four-input look-up table (lut) delay less than 1.0 ns with -8 speed grade) n high density (up to 43,200 usable, logic-only gates; or 99,400 gates including ram) n up to 480 user i/os (or2txxa and or2txxb i/os are 5 v tolerant to allow interconnection to both 3.3 v and 5 v devices, selectable on a per-pin basis) n four 16-bit look-up tables and four latches/flip-flops per pfu, nibble-oriented for implementing 4-, 8-, 16-, and/or 32-bit (or wider) bus structures n eight 3-state buffers per pfu for on-chip bus structures n fast, on-chip user sram has features to simplify ram design and increase ram speed: asynchronous single port: 64 bits/pfu synchronous single port: 64 bits/pfu synchronous dual port: 32 bits/pfu n improved ability to combine pfus to create larger ram structures using write-port enable and 3-state buffers n fast, dense multipliers can be created with the multiplier mode (4 x 1 multiplier/pfu): 8 x 8 multiplier requires only 16 pfus 30% increase in speed n flip-flop/latch options to allow programmable priority of synchronous set/reset vs. clock enable n enhanced cascadable nibble-wide data path capabilities for adders, subtractors, counters, multipliers, and comparators including internal fast-carry operation n innovative, abundant, and hierarchical nibble- oriented routing resources that allow automatic use of internal gates for all device densities without sacrificing performance n upward bit stream compatible with the orca at t 2 c x x / att2txx series of devices n pinout-compatible with new orca series 3 fpgas n ttl or cmos input levels programmable per pin for the or2cxxa (5 v) devices n individually programmable drive capability: 12 ma sink/6 ma source or 6 ma sink/3 ma source n built-in boundary scan ( ieee *1149.1 jtag) and 3-state all i/o pins, (ts_all) testability functions n multiple configuration options, including simple, low pin- count serial roms, and peripheral or jtag modes for in- system programming (isp) n full pci bus compliance for all devices n supported by industry-standard cae tools for design entry, synthesis, and simulation with orca foundry development system support (for back-end implementa- tion) n new, added features (or2txxb) have: more i/o per package than the or2txxa family no dedicated 5 v supply (v dd 5) faster configuration speed (40 mhz) pin selectable i/o clamping diodes provide 5v or 3.3v pci compliance and 5v tolerance full pci bus compliance in both 5v and 3.3v pci sys- tems * ieee is a registered trademark of the institute of electrical and electronics engineers, inc. table 1 . orca series 2 fpgas * the first number in the usable gates column assumes 48 gates per pfu (12 gates per four-input lut/ff pair) for logic-only desi gns. the second number assumes 30% of a design is ram. pfus used as ram are counted at four gates per bit, with each pfu capable of implementing a 16 x 4 ram (or 256 gates) per pfu. device usable gates* # luts registers max user ram bits user i/os array size or2c04a/or2t04a 4,80011,000 400 400 6,400 160 10 x 10 or2c06a/or2t06a 6,90015,900 576 576 9,216 192 12 x 12 or2c08a/or2t08a 9,40021,600 784 724 12,544 224 14 x 14 or2c10a/or2t10a 12,30028,300 1024 1024 16,384 256 16 x 16 or2c12a/or2t12a 15,60035,800 1296 1296 20,736 288 18 x 18 or2c15a/or2t15a/or2t15b 19,20044,200 1600 1600 25,600 320 20 x 20 or2c26a/or2t26a 27,60063,600 2304 2304 36,864 384 24 x 24 or2c40a/or2t40a/or2t40b 43,20099,400 3600 3600 57,600 480 30 x 30
data sheet orca series 2 fpgas june 1999 2 lucent technologies inc. table of contents contents page contents page features ...................................................................... 1 description................................................................... 3 orca foundry development system overview......... 5 architecture ................................................................. 5 programmable logic cells .......................................... 5 programmable function unit ................................... 5 look-up table operating modes ............................ 7 latches/flip-flops ................................................. 15 plc routing resources ........................................ 17 plc architectural description................................ 22 programmable input/output cells ............................. 25 inputs ..................................................................... 25 outputs .................................................................. 26 5 v tolerant i/o (or2txxb) .................................. 27 pci compliant i/o.................................................. 27 pic routing resources ......................................... 28 pic architectural description................................. 29 plc-pic routing resources ................................. 30 interquad routing ...................................................... 32 subquad routing (or2c40a/or2t40a only)...... 34 pic interquad (mid) routing ................................. 36 programmable corner cells ...................................... 37 programmable routing.......................................... 37 special-purpose functions.................................... 37 clock distribution network ........................................ 37 primary clock ........................................................ 37 secondary clock ................................................... 38 selecting clock input pins ..................................... 39 fpga states of operation......................................... 40 initialization............................................................ 40 configuration ......................................................... 41 start-up ................................................................. 42 reconfiguration ..................................................... 42 partial reconfiguration .......................................... 43 other configuration options .................................. 43 configuration data format ........................................ 43 using orca foundry to generate configuration ram data..................................... 44 configuration data frame ..................................... 44 bit stream error checking......................................... 47 fpga configuration modes....................................... 47 master parallel mode............................................. 47 master serial mode ............................................... 48 asynchronous peripheral mode ............................ 49 synchronous peripheral mode .............................. 49 slave serial mode ................................................. 50 slave parallel mode............................................... 50 daisy chain ........................................................... 51 special function blocks ............................................ 52 single function blocks .......................................... 52 boundary scan ...................................................... 54 boundary-scan instructions...................................55 orca boundary-scan circuitry ............................56 orca timing characteristics....................................60 estimating power dissipation ....................................61 or2cxxa...............................................................61 or2txxa ...............................................................63 or2t15b and or2t40b.......................................65 pin information ..........................................................66 pin descriptions.....................................................66 package compatibility ...........................................68 compatibility with series 3 fpgas ........................70 package thermal characteristics............................126 qja ......................................................................126 yjc.......................................................................126 qjc......................................................................126 qjb......................................................................126 package coplanarity ...............................................127 package parasitics ..................................................127 absolute maximum ratings .....................................129 recommended operating conditions......................129 electrical characteristics .........................................130 timing characteristics .............................................132 series 2................................................................160 measurement conditions.........................................169 output buffer characteristics...................................170 or2cxxa.............................................................170 or2txxa .............................................................171 or2txxb .............................................................172 package outline drawings ......................................173 terms and definitions ..........................................173 84-pin plcc........................................................174 100-pin tqfp......................................................175 144-pin tqfp......................................................176 160-pin qfp ........................................................177 208-pin sqfp......................................................178 208-pin sqfp2....................................................179 240-pin sqfp......................................................180 240-pin sqfp2....................................................181 256-pin pbga .....................................................182 304-pin sqfp......................................................183 304-pin sqfp2....................................................184 352-pin pbga .....................................................185 432-pin ebga .....................................................186 ordering information................................................187 index ........................................................................189
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 3 description the orca series 2 series of sram-based fpgas are an enhanced version of the att2c/2t architecture. the latest orca series includes patented architectural enhancements that make functions faster and easier to design while conserving the use of plcs and routing resources. the series 2 devices can be used as drop-in replace- ments for the att2cxx/att2txx series, respectively, and they are also bit stream compatible with each other. the usable gate counts associated with each series are provided in table 1. both series are offered in a variety of packages, speed grades, and tempera- ture ranges. the orca series fpga consists of two basic ele- ments: programmable logic cells (plcs) and program- mable input/output cells (pics). an array of plcs is surrounded by pics as shown in figure 1. each plc contains a programmable function unit (pfu). the plcs and pics also contain routing resources and configuration ram. all logic is done in the pfu. each pfu contains four 16-bit look-up tables (luts) and four latches/flip-flops (ffs). the plc architecture provides a balanced mix of logic and routing that allows a higher utilized gate/pfu than alternative architectures. the routing resources carry logic signals between pfus and i/o pads. the routing in the plc is symmetrical about the horizontal and ver- tical axes. this improves routability by allowing a bus of signals to be routed into the plc from any direction. some examples of the resources required and the per- formance that can be achieved using these devices are represented in table 2. table 2 . orca series 2 system performance 1. implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. implemented using two 16 x 12 roms and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 pfus contain only pi pelining registers). 4. implemented using 16 x 4 synchronous single-port ram mode allowing both read and write per clock cycle, including write/read address multiplexer. 5. implemented using 16 x 4 synchronous single-port ram mode allowing either read or write per clock cycle, including write/read address mul- tiplexer. 6. implemented using 16 x 2 synchronous dual-port ram mode. 7. or2txxb available only in -7 and -8 speeds only. 8. speed grades of -5, -6, and -7 are for or2txxa devices only. function # pfus speed grade unit -2a -3a -4a -5a -6a -7a -7b -8b 16-bit loadable up/down counter 4 51.0 66.7 87.0 104.2 129.9 144.9 131.6 149.3 mhz 16-bit accumulator 4 51.0 66.7 87.0 104.2 129.9 144.9 131.6 149.3 mhz 8 x 8 parallel multiplier: multiplier mode, unpipelined 1 rom mode, unpipelined 2 multiplier mode, pipelined 3 22 9 44 14.2 41.5 50.5 19.3 55.6 69.0 25.1 71.9 82.0 31.0 87.7 103.1 36.0 107.5 125.0 40.3 122.0 142.9 37.7 103.1 123.5 44.8 120.5 142.9 mhz mhz mhz 32 x 16 ram: single port (read and write/ cycle) 4 single port 5 dual port 6 9 9 16 21.8 38.2 38.2 28.6 52.6 52.6 36.2 69.0 83.3 53.8 92.6 92.6 53.8 92.6 92.6 62.5 96.2 96.2 57.5 97.7 97.7 69.4 112.4 112.4 mhz mhz mhz 36-bit parity check (internal) 4 13.9 11.0 9.1 7.4 5.6 5.2 6.1 5.1 ns 32-bit address decode (internal) 3.25 12.3 9.5 7.5 6.1 4.6 4.3 4.8 4.0 ns
data sheet orca series 2 fpgas june 1999 4 lucent technologies inc. description (continued) the fpgas functionality is determined by internal configuration ram. the fpgas internal initialization/configura- tion circuitry loads the configuration data at powerup or under system control. the ram is loaded by using one of several configuration modes. the configuration data resides externally in an eeprom, eprom, or rom on the circuit board, or any other storage media. serial roms provide a simple, low pin count method for configuring fpgas, while the peripheral and jtag configuration modes allow for easy, in-system programming (isp). 5-6779(f) figure 1. series 2 array pl9 pl8 pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl13 pl12 pl11 pr12 pr11 pr9 pr8 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr13 pr18 pr17 pr16 pr15 pr14 rmid pr10 pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt11 pt12 r1c1 r1c2 r1c3 r1c4 r1c5 r1c6 r1c7 r1c8 r1c9 r1c10 r1c18 r1c17 r1c16 r1c15 r1c14 r1c13 r1c12 r1c11 pt13 pt14 pt15 pt16 pt17 pt18 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pb10 pb11 pb12 pl18 pl17 pl16 pl15 pl14 pb13 pb14 pb15 pb16 pb17 pb18 pl10 bmid pt10 viq r2c1 r2c2 r2c3 r2c4 r2c5 r2c6 r2c7 r2c8 r2c9 r2c10 r3c1 r3c2 r3c3 r3c4 r3c5 r3c6 r3c7 r3c8 r3c9 r3c10 r4c1 r4c2 r4c3 r4c4 r4c5 r4c6 r4c7 r4c8 r4c9 r4c10 r5c1 r5c2 r5c3 r5c4 r5c5 r5c6 r5c7 r5c8 r5c9 r5c10 r6c1 r6c2 r6c3 r6c4 r6c5 r6c6 r6c7 r6c8 r6c9 r6c10 r7c1 r7c2 r7c3 r7c4 r7c5 r7c6 r7c7 r7c8 r7c9 r7c10 r8c1 r8c2 r8c3 r8c4 r8c5 r8c6 r8c7 r8c8 r8c9 r8c10 r9c1 r9c2 r9c3 r9c4 r9c5 r9c6 r9c7 r9c8 r9c9 r9c10 r10c1 r10c2 r10c3 r10c4 r10c5 r10c6 r10c7 r10c8 r10c9 r10c10 r2c18 r2c17 r2c16 r2c15 r2c14 r2c13 r2c12 r2c11 r3c18 r3c17 r13c16 r3c15 r3c14 r3c13 r3c12 r3c11 r4c18 r4c17 r4c16 r4c15 r4c14 r4c13 r4c12 r4c11 r5c18 r5c17 r5c16 r5c15 r5c14 r5c13 r5c12 r5c11 r6c18 r6c17 r6c16 r6c15 r6c14 r6c13 r6c12 r6c11 r7c18 r7c17 r7c16 r7c15 r7c14 r7c13 r7c12 r7c11 r8c18 r8c17 r8c16 r8c15 r8c14 r8c13 r8c12 r8c11 r9c18 r9c17 r9c16 r9c15 r9c14 r9c13 r9c12 r9c11 r10c18 r10c17 r10c16 r10c15 r10c14 r10c13 r10c12 r10c11 r18c18 r18c17 r18c16 r18c15 r18c14 r18c13 r18c12 r18c11 r17c18 r17c17 r17c16 r17c15 r17c14 r17c13 r17c12 r17c11 r16c18 r16c17 r16c16 r16c15 r16c14 r16c13 r16c12 r16c11 r15c18 r15c17 r15c16 r15c15 r15c14 r15c13 r15c12 r15c11 r14c18 r14c17 r14c16 r14c15 r14c14 r14c13 r14c12 r14c11 r13c18 r13c17 r13c16 r13c15 r13c14 r13c13 r13c12 r13c11 r12c18 r12c17 r12c16 r12c15 r12c14 r12c13 r12c12 r12c11 r11c18 r11c17 r11c16 r11c15 r11c14 r11c13 r11c12 r11c11 r18c10 r18c9 r18c8 r18c7 r18c6 r18c5 r18c4 r18c3 r18c2 r18c1 r17c10 r17c9 r17c8 r17c7 r17c6 r17c5 r17c4 r17c3 r17c2 r17c1 r16c10 r16c9 r16c8 r16c7 r16c6 r16c5 r16c4 r16c3 r16c2 r16c1 r15c10 r15c9 r15c8 r15c7 r15c6 r15c5 r15c4 r15c3 r15c2 r15c1 r14c10 r14c9 r14c8 r14c7 r14c6 r14c5 r14c4 r14c3 r14c2 r14c1 r13c10 r13c9 r13c8 r13c7 r13c6 r13c5 r13c4 r13c3 r13c2 r13c1 r12c10 r12c9 r12c8 r12c7 r12c6 r12c5 r12c4 r12c3 r12c2 r12c1 r11c10 r11c9 r11c8 r11c7 r11c6 r11c5 r11c4 r11c3 r11c2 r11c1 hiq tmid lmid
lucent technologies inc. 5 data sheet june 1999 orca series 2 fpgas orca foundry development system overview the orca foundry development system interfaces to front-end design entry tools and provides the tools to produce a configured fpga. in the design flow, the user defines the functionality of the fpga at two points: at design entry and at the bit stream generation stage. following design entry, the development systems map, place, and route tools translate the netlist into a routed fpga. its bit stream generator is then used to generate the configuration data which is loaded into the fpgas internal configuration ram. when using the bit stream generator, the user selects options that affect the func- tionality of the fpga. combined with the front-end tools, orca foundry produces configuration data that implements the various logic and routing options dis- cussed in this data sheet. architecture the orca series fpga is comprised of two basic elements: plcs and pics. figure 1 shows an array of programmable logic cells (plcs) surrounded by pro- grammable input/output cells (pics). the series 2 has plcs arranged in an array of 20 rows and 20 columns. pics are located on all four sides of the fpga between the plcs and the ic edge. the location of a plc is indicated by its row and col- umn so that a plc in the second row and third column is r2c3. pics are indicated similarly, with pt (top) and pb (bottom) designating rows and pl (left) and pr (right) designating columns, followed by a number. the routing resources and configuration ram are not shown, but the interquad routing blocks (hiq, viq) present in the series 2 series are shown. each pic contains the necessary i/o buffers to inter- face to bond pads. the pics also contain the routing resources needed to connect signals from the bond pads to/from plcs. the pics do not contain any user- accessible logic elements, such as flip-flops. combinatorial logic is done in look-up tables (luts) located in the pfu. the pfu can be used in different modes to meet different logic requirements. the luts configurable medium-/large-grain architecture can be used to implement from one to four combinatorial logic functions. the flexibility of the lut to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count/pfu. the luts can be programmed to operate in one of three modes: combinatorial, ripple, or memory. in com- binatorial mode, the luts can realize any four-, five-, or six-input logic functions. in ripple mode, the high- speed carry logic is used for arithmetic functions, the new multiplier function, or the enhanced data path functions. in memory mode, the luts can be used as a 16 x 4 read/write or read-only memory (asynchronous mode or the new synchronous mode) or a new 16 x 2 dual-port memory. programmable logic cells the programmable logic cell (plc) consists of a pro- grammable function unit (pfu) and routing resources. all plcs in the array are identical. the pfu, which con- tains four luts and four latches/ffs for logic imple- mentation, is discussed in the next section. programmable function unit the pfus are used for logic. each pfu has 19 exter- nal inputs and six outputs and can operate in several modes. the functionality of the inputs and outputs depends on the operating mode. the pfu uses three input data buses (a[4:0], b[4:0], wd[3:0]), four control inputs (c0, ck, ce, lsr), and a carry input (cin); the last is used for fast arithmetic functions. there is a 5-bit output bus (o[4:0]) and a carry-out (cout). 5-2750(f).r3 figure 2. pfu ports programmable logic cell (plc) wd3 wd2 wd1 wd0 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 o4 o3 o2 o1 o0 programmable function unit ce lsr c0 ck (routing resources, configuration ram) cin (pfu) cout
data sheet orca series 2 fpgas june 1999 6 lucent technologies inc. programmable logic cells (continued)) key: c = controlled by configuration ram. figure 3. simplified pfu diagram 5-4573(f) a4 a3 a2 a1 a4 a3 a2 a1 qlut3 a0 carry carry a3 a2 a1 a0 qlut2 b4 b3 b2 b1 b4 b3 b2 b1 qlut1 b0 carry carry b3 b2 b1 b0 qlut0 cin c0 lsr gsr wd[3:0] ck cken tri pfu_xor b4 a4 pfu_nand pfu_mux c c c c wd3 wd2 wd1 wd0 c c c t t t t reg3 sr en reg2 sr en reg1 sr en reg0 sr en o4 o3 o2 o1 o0 f3 c c cout f2 f1 f0 d0 d1 d2 d3 q0 q1 q2 q3 c t t t t c figure 2 and figure 3 show high-level and detailed views of the ports in the pfu, respectively. the ports are referenced with a two- to four-character suffix to a pfus location. as mentioned, there are two 5-bit input data buses (a[4:0] and b[4:0]) to the lut, one 4-bit input data bus (wd[3:0]) to the latches/ffs, and an output data bus (o[4:0]). figure 3 shows the four latches/ffs (reg[3:0]) and the 64-bit look-up table (qlut[3:0]) in the pfu. the pfu does combinatorial logic in the lut and sequential logic in the latches/ffs. the lut is static random access memory (sram) and can be used for read/ write or read-only memory. the eight 3-state buffers found in each plc are also shown, although they actu- ally reside external to the pfu. each latch/ff can accept data from the lut. alterna- tively, the latches/ffs can accept direct data from wd[3:0], eliminating the lut delay if no combinatorial function is needed. the lut outputs can bypass the latches/ffs, which reduces the delay out of the pfu. it is possible to use the lut and latches/ffs more or less independently. for example, the latches/ffs can be used as a 4-bit shift register, and the lut can be used to detect when a register has a particular pattern in it.
lucent technologies inc. 7 data sheet june 1999 orca series 2 fpgas programmable logic cells (continued) table 3 lists the basic operating modes of the lut. the operating mode affects the functionality of the pfu input and output ports and internal pfu routing. for example, in some operating modes, the wd[3:0] inputs are direct data inputs to the pfu latches/ffs. in the dual 16 x 2 memory mode, the same wd[3:0] inputs are used as a 4-bit data input bus into lut memory. the pfu is used in a variety of modes, as illustrated in figures 4 through 11, and it is these specific modes that are most relevant to pfu functionality. pfu control inputs the four control inputs to the pfu are clock (ck), local set/reset (lsr), clock enable (ce), and c0. the ck, ce, and lsr inputs control the operation of all four latches in the pfu. an active-low global set/reset (gsrn) signal is also available to the latches/ffs in every pfu. their operation is discussed briefly here, and in more detail in the latches/flip-flops section. the polarity of the control inputs can be inverted. the ck input is distributed to each pfu from a vertical or horizontal net. the ce input inhibits the latches/ffs from responding to data inputs. the ce input can be disabled, always enabling the clock. each latch/ff can be independently programmed to be set or reset by the lsr and the global set/reset (gsrn) signals. each pfus lsr input can be configured as synchronous or asynchronous. the gsrn signal is always asynchro- nous. the lsr signal applies to all four latches/ffs in a pfu. the lsr input can be disabled (the default). the asynchronous set/reset is dominant over clocked inputs. the c0 input is used as an input into the special pfu gates for wide functions in combinatorial logic mode. in the memory modes, this input is also used as the write-port enable input. the c0 input can be disabled (the default). look-up table operating modes the look-up table (lut) can be configured to operate in one of three general modes: n combinatorial logic mode n ripple mode n memory mode the combinatorial logic mode uses a 64-bit look-up table to implement boolean functions. the two 5-bit logic inputs, a[4:0] and b[4:0], and the c0 input are used as lut inputs. the use of these ports changes based on the pfu operating mode. the functionality of the lut is determined by its operat- ing mode. the entries in table 3 show the basic modes of operation for combinatorial logic, ripple, and memory functions in the lut. depending on the operating mode, the lut can be divided into sub-luts. the lut is comprised of two 32-bit half look-up tables, hluta and hlutb. each half look-up table (hlut) is com- prised of two quarter look-up tables (qluts). hluta consists of qlut2 and qlut3, while hlutb consists of qlut0 and qlut1. the outputs of qlut0, qlut1, qlut2, and qlut3 are f0, f1, f2, and f3, respec- tively. table 3. look-up table operating modes for combinatorial logic, the lut can be used to do any single function of six inputs, any two functions of five inputs, or four functions of four inputs (with some inputs shared), and three special functions based on the two five-input functions and c0. mode function f4a two functions of four inputs, some inputs shared (qlut2/qlut3) f4b two functions of four inputs, some inputs shared (qlut0/qlut1) f5a one function of five inputs (hluta) f5b one function of five inputs (hlutb) r 4-bit ripple (lut) ma 16 x 2 asynchronous memory (hluta) mb 16 x 2 asynchronous memory (hlutb) sspm 16 x 4 synchronous single-port memory sdpm 16 x 2 synchronous dual-port memory
8 lucent technologies inc. data sheet orca series 2 fpgas june 1999 programmable logic cells (continued) the lut ripple mode operation offers standard arith- metic functions, such as 4-bit adders, subtractors, adder/subtractors, and counters. in the orca series 2, there are two new ripple modes available. the first new mode is a 4 x 1 multiplier, and the second is a 4-bit comparator. these new modes offer the advantages of faster speeds as well as denser logic capabilities. when the lut is configured to operate in the memory mode, a 16 x 2 asynchronous memory fits into an hlut. both the ma and mb modes were available in previous orca architectures, and each mode can be configured in an hlut separately. in the series 2, there are two new memory modes available. the first is a 16 x 4 synchronous single-port memory (sspm), and the second is a 16 x 2 synchronous dual-port memory (sdpm). these new modes offer easier implementa- tion, faster speeds, denser rams, and a dual-port capability that wasnt previously offered as an option in the att2cxx/att2txx families. if the lut is configured to operate in the ripple mode, it cannot be used for basic combinatorial logic or memory functions. in modes other than the ripple, sspm, and sdpm modes, combinations of operating modes are possible. for example, the lut can be configured as a 16 x 2 ram in one hlut and a five-input combinatorial logic function in the second hlut. this can be done by configuring hluta in the ma mode and hlutb in the f5b mode (or vice versa). f4a/f4b modetwo four-input functions each hlut can be used to implement two four-input combinatorial functions, but the total number of inputs into each hlut cannot exceed five. the two qluts within each hlut share three inputs. in hluta, the a1, a2, and a3 inputs are shared by qlut2 and qlut3. similarly, in hlutb, the b1, b2, and b3 inputs are shared by qlut0 and qlut1. the four outputs are f0, f1, f2, and f3. the results can be routed to the d0, d1, d2, and d3 latch/ff inputs or as an output of the pfu. the use of the lut for four functions of up to four inputs each is given in figure 4. f5a/f5b modeone five-input variable function each hlut can be used to implement any five-input combinatorial function. the input ports are a[4:0] and b[4:0], and the output ports are f0 and f3. one five or less input function is input into a[4:0], and the second five or less input function is input into b[4:0]. the results are routed to the latch/ff d0 and latch/ff d3 inputs, or as a pfu output. the use of the lut for two independent functions of up to five inputs is shown in figure 5. in this case, the lut is configured in the f5a and f5b modes. as a variation, the lut can do one function of up to five input variables and two four-input functions using f5a and f4b modes or f4a and f5b modes. 5-2753(f).r2 figure 4. f4 modefour functions of four- input variables 5-2845(f).r2 figure 5. f5 modetwo functions of five-input variables qlut2 a3 a3 a2 a1 a0 a2 a1 a0 f2 qlut3 a4 a4 a3 a2 a1 a3 a2 a1 f3 hluta qlut0 b3 b3 b2 b1 b0 b2 b1 b0 f0 qlut1 b4 b4 b3 b2 b1 b3 b2 b1 f1 hlutb qlut3 qlut2 f3 qlut1 qlut0 b4 b3 b2 b1 b0 f0 wea a3 a2 a1 a0 b4 b3 b2 b1 b0 a4 a3 a2 a1 a0 hluta hlutb c0 wpe wd3 wd2 wd3 wd2 f2
lucent technologies inc. 9 data sheet june 1999 orca series 2 fpgas programmable logic cells (continued) f5m and f5x modesspecial function modes the pfu contains logic to implement two special func- tion modes which are variations on the f5 mode. as with the f5 mode, the lut implements two indepen- dent five-input functions. figure 6 and figure 7 show the schematics for f5m and f5x modes, respectively. the f5x and f5m functions differ from the basic f5a/ f5b functions in that there are three logic gates which have inputs from the two 5-input lut outputs. in some cases, this can be used for faster and/or wider logic functions. as can be seen, two of the three inputs into the nand, xor, and mux gates, f0 and f3, are from the lut. the third input is from the c0 input into pfu. since the c0 input bypasses the luts, it has a much smaller delay through the pfu than for all other inputs into the special pfu gates. this allows multiple pfus to be cascaded together while reducing the delay of the criti- cal path through the pfus. the output of the first spe- cial function (either xor or mux) is f1. since the xor and mux share the f1 output, the f5x and f5m modes are mutually exclusive. the output of the nand pfu gate is f2 and is always available in either mode. to use either the f5m or f5x functions, the lut must be in the f5a/f5b mode; i.e., only 5-input luts allowed. in both the f5x and f5m functions, the out- puts of the five-input combinatorial functions, f0 and f3, are also usable simultaneously with the special pfu gate outputs. the output of the mux is: f1 = (hluta & c0) + (hlutb & c0 ) f1 = (f3 & c0) + (f0 & c0 ) the output of the exclusive or is: f1 = hluta ? hlutb ? c0 f1 = f3 ? f0 ? c0 the output of the nand is: f2 = hluta & hlutb & c0 f2 = f3 & f0 & c0 5-2754(f).r3 figure 6. f5m modemultiplexed function of two independent five-input variable functions 5-2755(f).r2 figure 7. f5x modeexclusive or function of two independent five-input variable functions qlut3 qlut2 a4 a4 a3 a2 a1 a0 a3 a2 a1 a0 qlut1 qlut0 b4 b4 b3 b2 b1 b0 b3 b2 b1 b0 c0 f3 f0 f1 f0 f2 f3 a4 a4 a3 a2 a1 a0 a3 a2 a1 a0 b4 b4 b3 b2 b1 b0 b3 b2 b1 b0 c0 f3 f0 f1 f0 f2 f3 hluta hlutb
10 lucent technologies inc. data sheet orca series 2 fpgas june 1999 programmable logic cells (continued) 5-2751(f).r3 figure 8. f5m modeone six-input variable function f5m modeone six-input variable function the lut can be used to implement any function of six- input variables. as shown in figure 8, five input signals (a[4:0]) are routed into both the a[4:0] and b[4:0] ports, and the c0 port is used for the sixth input. the output port is f1. ripple mode the lut can do nibble-wide ripple functions with high- speed carry logic. each qlut has a dedicated carry- out net to route the carry to/from the adjacent qlut. using the internal carry circuits, fast arithmetic and counter functions can be implemented in one pfu. similarly, each pfu has carry-in (cin) and carry-out (cout) ports for fast-carry routing between adjacent pfus. the ripple mode is generally used in operations on two 4-bit buses. each qlut has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. a single bit is rippled from the previous qlut and is used as input into the current qlut. for qlut0, the ripple input is from the pfu cin port. the cin data can come from either the fast-carry routing or the pfu input b4, or it can be tied to logic 1 or logic 0. the resulting output and ripple output are calculated by using generate/propagate circuitry. in ripple mode, the two operands are input into a[3:0] and b[3:0]. the four result bits, one per qlut, are f[3:0] (see figure 9). the ripple output from qlut3 can be routed to dedi- cated carry-out circuitry into any of four adjacent plcs, or it can be placed on the o4 pfu output, or both. this allows the plcs to be cascaded in the ripple mode so that nibble-wide ripple functions can be expanded eas- ily to any length. 5-2756(f).r32 figure 9. ripple mode the ripple mode can be used in one of four submodes. the first of these is adder/subtractor mode . in this mode, each qlut generates two separate outputs. one of the two outputs selects whether the carry-in is to be propagated to the carry-out of the current qlut or if the carry-out needs to be generated. the result of this selection is placed on the carry-out signal, which is connected to the next qlut or the cout signal, if it is the last qlut (qlut3). the other qlut output creates the result bit for each qlut that is connected to f[3:0]. if an adder/subtractor is needed, the control signal to select addition or sub- traction is input on a4. the result bit is created in one- half of the qlut from a single bit from each input bus, along with the ripple input bit. these inputs are also used to create the programmable propagate. qlut3 qlut2 a4 a4 a3 a2 a1 a0 a3 a2 a1 a0 qlut1 qlut0 b4 b4 b3 b2 b1 b0 b3 b2 b1 b0 c0 f3 f0 f1 qlut3 b3 b3 a3 a3 f3 qlut2 b2 b2 a2 a2 f2 qlut1 b1 b1 a1 a1 f1 qlut0 b0 b0 a0 a0 f0 cin cin cout cout
lucent technologies inc. 11 data sheet june 1999 orca series 2 fpgas programmable logic cells (continued) the second submode is the counter submode (see figure 10). the present count is supplied to input a[3:0], and then output f[3:0] will either be incre- mented by one for an up counter or decremented by one for a down counter. if an up counter or down counter is needed, the control signal to select the direc- tion (up or down) is input on a4. generally, the latches/ ffs in the same pfu are used to hold the present count value. 5-4643(f).r1 figure 10. counter submode with flip-flops in the third submode, multiplier submode , a single pfu can affect a 4 x 1-bit multiply and sum with a par- tial product (see figure 11). the multiplier bit is input at a4, and the multiplicand bits are input at b[3:0], where b3 is the most significant bit (msb). a[3:0] contains the partial product (or other input to be summed) from a previous stage. if a4 is logical 1, the multiplicand is added to the partial product. if a4 is logical zero, zero is added to the partial product, which is the same as passing the partial product. cin can hold the carry-in from the less significant pfus if the multiplicand is wider than 4 bits, and cout holds any carry-out from the addition, which may then be used as part of the product or routed to another pfu in multiplier mode for multiplicand width expansion. figure 11. multiplier submode ripple modes fourth submode features equality comparators , where one 4-bit bus is input on b[3:0], another 4-bit bus is input on b[3:0], and the carry-in is tied to 0 inside the pfu. the carry-out (|) signal will be 0 if a = b or will be 1 if a | b. if larger than 4 bits, the carry-out (|) signal can be cascaded using fast-carry logic to the carry-in of any adjacent pfu. comparators for greater than or equal or less than (>, =, <) continue to be supported using the ripple mode subtractor. the use of this submode could be shown using figure 9 with cin tied to 0. dq cout lut a3 qlut3 f3 q3 cout dq a2 qlut2 f2 q2 dq a1 qlut1 f1 q1 dq a0 qlut0 f0 q0 cin cin + 10 a3 b3 0 a4 cout f3 + a2 b2 f2 + a1 b1 f1 + a0 b0 f0 cin 10 0 10 0 10 0 5-4620(f)
12 lucent technologies inc. data sheet orca series 2 fpgas june 1999 programmable logic cells (continued) asynchronous memory modesma and mb the lut in the pfu can be configured as either read/ write or read-only memory. a read/write address (a[3:0], b[3:0]), write data (wd[1:0], wd[3:2]), and two write-enable (we) ports are used for memory. in asyn- chronous memory mode, each hlut can be used as a 16 x 2 memory. each hlut is configured indepen- dently, allowing functions such as a 16 x 2 memory in one hlut and a logic function of five input variables or less in the other hlut. figure 12 illustrates the use of the lut for a 16 x 4 memory. when the luts are used as memory, there are independent address, input data, and output data buses. if the lut is used as a 16 x 4 read/write mem- ory, the a[3:0] and b[3:0] ports are address inputs (a[3:0]). the a4 and b4 ports are write-enable (we) signals. the wd[3:0] inputs are the data inputs. the f[3:0] data outputs can be routed out on the o[4:0] pfu outputs or to the latch/ff d[3:0] inputs. 5-2757(f).r3 figure 12. ma/mb mode16 x 4 ram to increase memory word depth above 16 (e.g., 32 x 4), two or more plcs can be used. the address and write data inputs for the two or more plcs are tied together (bit by bit), and the data outputs are routed through the four 3-statable bidis available in each pfu and are then tied together (bit by bit). the control signal of the 3-statable bidis, called a ram bank-enable, is created from a decode of upper address bits. the ram bank-enable is then used to enable 4 bits of data from a plc onto the read data bus. the orca series 2 series also has a new and func- tion available for each pfu in ram mode. the inputs to this function are the write-enable (we) signal and the write-port enable (wpe) signal. the write-enable sig- nal is a4 for hluta and b4 for hlutb, while the other input into the and gates for both hluts is the write- port enable, input on c0 or cin. generally, the wpe input is driven by the same ram bank-enable signal that controls the bidis in each pfu. the selection of which ram bank to write data into does not require the use of luts from other pfus, as in previous orca architectures. this reduces the num- ber of pfus required for rams larger than 16 words in depth. note that if either hlut is in ma/mb mode, then the same wpe is active for both hluts. to increase the memorys word size (e.g., 16 x 8), two or more plcs are used again. the address, write- enable, and write-port enable of the plcs are tied together (bit by bit), and the data is different for each plc. increasing both the address locations and word size is done by using a combination of these two tech- niques. the lut can be used simultaneously for both memory and a combinatorial logic function. figure 13 shows the use of a lut implementing a 16 x 2 ram (hluta) and any function of up to five input variables (hlutb). 5-2845(f).a.r1 figure 13. ma/f5 mode16 x 2 memory and one function of five input variables a3 a3 a2 a1 a0 wd3 a2 a1 a0 wd3 f3 f2 wd2 wd2 wd1 wd0 b3 b2 b1 wd0 b3 b2 b1 f1 f0 b0 b0 wd1 a4 b4 wea web hluta hlutb wpe c0 c0 qlut3 qlut2 f3 qlut1 qlut0 b4 b3 b2 b1 b0 f0 wea a3 a2 a1 a0 b4 b3 b2 b1 b0 a4 a3 a2 a1 a0 hluta hlutb f2 wd3 wpe wd3 c0
lucent technologies inc. 13 data sheet june 1999 orca series 2 fpgas programmable logic cells (continued) synchronous memory modessspm and sdpm the ma/mb asynchronous memory modes described previously allow the pfu to perform as a 16 x 4 (64 bits) single-port ram. synchronously writing to this ram requires the write-enable control signal to be gated with the clock in another pfu to create a write pulse. to simplify this functionality, the series 2 devices contain a synchronous single-port memory (sspm) mode, where the generation of the write pulse is done in each pfu. with sspm mode, the entire lut becomes a 16 x 4 ram, as shown in figure 14. in this mode, the input ports are write enable (we), write-port enable (wpe), read/write address (a[3:0]), and write data (wd[3:0]). to synchronously write the ram, we (input into a4) and wpe (input into either c0 or cin) are latched and anded together. the result of this and function is sent to a pulse generator in the lut, which writes the ram synchronous to the ram clock. this ram clock is the same one sent to the pfu latches/ffs; however, if nec- essary, it can be programmably inverted. 5-4642(f).r1 figure 14. sspm mode16 x 4 synchronous single-port memory the write address (wa[3:0]) and write data (wd[3:0]) are also latched by the ram clock in order to simplify the timing. reading data from the ram is done asyn- chronously; thus, the read address (ra[3:0]) is not latched. the result from the read operation is placed on the lut outputs (f[3:0]). the f[3:0] data outputs can be routed out of the pfu or sent to the latch/ff d[3:0] inputs. there are two ways to use the latches/ffs in conjunc- tion with the sspm. if the phase of the latch/ff clock and the ram clock are the same, only a read address or write address can be supplied to the ram that meets the synchronous timing requirements of both the ram clock and latch/ff clock. therefore, either a write to the ram or a read from the ram can be done in each clock cycle, but not both. if the ram clock is inverted from the latch/ff clock, then both a write to the ram and a read from the ram can occur in each clock cycle. this is done by adding an external write address/read address multiplexer as shown in figure 15. the write address is supplied on the phase of the clock that allows for setup to the ram clock, and the read address is supplied on the phase of the clock that allows the read data to be set up to the latch/ff clock. if a higher-speed ram is required that allows both a read and write in each clock cycle, the synchronous dual-port memory mode (sdpm) can be used, since it does not require the use of an external multiplexer. 5-4644(f).r1 figure 15. sspm with read/write per clock cycle we wpe a4 dq dq cin, c0 a[3:0] wd[3:0] wr wa[3:0] ra[3:0] wd[3:2] hluta f3 f2 dq dq wr wa[3:0] ra[3:0] wd[1:0] hlutb f1 f0 write pulse generator a[3:0], b[3:0] wd[3:0] we a wd ram clk write address read address 0 1 wpe sspm clock dq pfu
data sheet orca series 2 fpgas june 1999 14 lucent technologies inc. programmable logic cells (continued) note: the lower address bits are not shown. figure 16. synchronous ram with write-port enable (wpe) upper address bits address decode lut1 bank_en1 upper address bits address decode lut2 bank_en2 wr di wpe do 16 x 4 ram + 4 buffers/pfu bidi dout 4 wr di wpe do 16 x 4 ram + 4 buffers/pfu din wr clk 4 bidi 4 4 5-4640(f) to increase memory word depth above 16 (e.g., 32 x 4), two or more plcs can be used. the address and write data inputs for the two or more plcs are tied together (bit by bit), and the data outputs are routed through the four 3-statable bidis available in each pfu. the bidi outputs are then tied together (bit by bit), as seen in figure 16. the control signals of the 3-statable bidis, called ram bank-enable (bank_en1 and bank_en2), are cre- ated from a decode of upper address bits. the ram bank-enable is then used to enable 4 bits of data from a plc onto the read data (dout) bus. the series 2 series now has a new and function avail- able for each pfu in ram mode. the inputs to this function are the write-enable (we) signal and the write- port enable (wpe) signal. the write-enable signal is input on a4, while the write-port enable is input on c0 or cin. generally, the wpe input is driven by the same ram bank-enable signal that controls the bidis in each pfu. the selection as to which ram bank to write data into does not require the use of luts from other pfus, as in previous orca architectures. this reduces the num- ber of pfus required for rams larger than 16 words in depth. a special use of this method can be to increase word depth to 32 words. since both the wpe input into the ram and the 3-state input into the bidi can be inverted, a decode of the one upper address bit is not required. instead, the bank-enable signal for both banks is tied to the upper address bit, with the wpe and 3-state inputs active-high for one bank and active- low for the other. to increase the memorys word size (e.g., 16 x 8), two or more plcs are used again. the address, write- enable, and write-port enable of the plcs are tied together (bit by bit), and the data is different for each plc. increasing both the address locations and word size is accomplished by using a combination of these two techniques.
lucent technologies inc. 15 data sheet june 1999 orca series 2 fpgas programmable logic cells (continued) 5-4641(f).r1 figure 17. sdpm mode16 x 2 synchronous dual-port memory the series 2 devices have added a second synchro- nous memory mode known as the synchronous dual- port memory (sdpm) mode. this mode writes data into the memory synchronously in the same manner described previously for sspm mode. the sdpm mode differs in that two separate 16 x 2 memories are created in each pfu that have the same we, wpe, write data (wd[1:0]), and write address (wa[3:0]) inputs, as shown in figure 17. the outputs of hluta (f[3:2]) operate the same way they do in sspm modethe read address comes directly from the a[3:0] inputs used to create the latched write address. the outputs of hlutb (f[1:0]) operate in a dual-port mode where the write address comes from the latched version of a[3:0], and the read address comes directly from ra[3:0], which is input on b[3:0]. since external multiplexing of the write address and read address is not required, extremely fast rams can be created. new system applications that require an interface between two different asynchronous clocks can also be implemented using the sdpm mode. an example of this is accomplished by creating fifos where one clock controls the synchronous write of data into the fifo, and the other clock controls the read address to allow reading of data at any time from the fifo. latches/flip-flops the four latches/ffs in the pfu can be used in a vari- ety of configurations. in some cases, the configuration options apply to all four latches/ffs in the pfu. for other options, each latch/ff is independently program- mable. table 4 summarizes these latch/ff options. the latches/ffs can be configured as either positive or negative level-sensitive latches, or positive or negative edge-triggered flip-flops. all latches/ffs in a given pfu share the same clock, and the clock to these latches/ ffs can be inverted. the input into each latch/ff is from either the corresponding qlut output (f[3:0]) or the direct data input (wd[3:0]). for latches/ffs located in the two outer rings of plcs, additional inputs are possible. these additional inputs are fast paths from i/o pads located in pics in the same row or column as the plcs. if the latch/ff is not located in the two outer rings of the plcs, the latch/ff input can also be tied to logic 0, which is the default. the four latch/ff outputs, q[3:0], can be placed on the five pfu outputs, o[4:0]. table 4. configuration ram controlled latch/ flip-flop operation the four latches/ffs in a pfu share the clock (ck), clock enable (ce), and local set/reset (lsr) inputs. when ce is disabled, each latch/ff retains its previous value when clocked. both the clock enable and lsr inputs can be inverted to be active-low. we wpe a4 dq dq cin, c0 wa[3:0] wd[1:0] wr wa[3:0] ra[3:0] wd[1:0] hluta f3 f2 dq dq wr wa[3:0] ra[3:0] wd[1:0] hlutb f1 f0 write pulse generator a[3:0] wd[1:0] ra[3:0] b[3:0] sspm output sdpm output function options functionality common to all latch/ffs in pfu lsr operation asynchronous or synchronous clock polarity noninverted or inverted front-end select direct (wd[3:0]) or from lut (f[3:0]) lsr priority either lsr or ce has priority functionality set individually in each latch/ff in pfu latch/ff mode latch or flip-flop set/reset mode set or reset
data sheet orca series 2 fpgas june 1999 16 lucent technologies inc. programmable logic cells (continued) the set/reset operation of the latch/ff is controlled by two parameters: reset mode and set/reset value. when the global set/reset (gsrn) or local set/reset (lsr) are inactive, the storage element operates normally as a latch or ff. the reset mode is used to select a synchro- nous or asynchronous lsr operation. if synchronous, lsr is enabled only if clock enable (ce) is active. for the series 2 series, a new option called the lsr prior- ity allows the synchronous lsr to have priority over the ce input, thereby setting or resetting the ff indepen- dent of the state of ce. the clock enable is supported on ffs, not latches. the clock enable function is imple- mented by using a two-input multiplexer on the ff input, with one input being the previous state of the ff and the other input being the new data applied to the ff. the select of this two-input multiplexer is clock enable (ce), which selects either the new data or the previous state. when ce is inactive, the ff output does not change when the clock edge arrives. the gsrn signal is only asynchronous, and it sets/ resets all latches/ffs in the fpga based upon the set/ reset configuration bit for each latch/ff. the set/reset value determines whether gsrn and lsr are set or reset inputs. the set/reset value is independent for each latch/ff. if the local set/reset is not needed, the latch/ff can be configured to have a data front-end select. two data inputs are possible in the front-end select mode, with the lsr signal used to select which data input is used. the data input into each latch/ff is from the output of its associated qlut f[3:0] or direct from wd[3:0], bypassing the lut. in the front-end data select mode, both signals are available to the latches/ffs. for plcs that are in the two outside rows or columns of the array, the latch/ffs can have two inputs in addition to the f and wd inputs mentioned above. one input is from an i/o pad located at the pic closest to either the left or right of the given plc (if the plc is in the left two columns or right two columns of the array). the other input is from an i/o pad located at the closest pic either above or below the given plc (if the plc is in the top or the bottom two rows). it should be noted that both inputs are available for a 2 x 2 array of plcs in each corner of the array. for the entire array of plcs, if either or both of these inputs is unavailable, the latch/ ff data input can be tied to a logic 0 instead (the default). to speed up the interface between signals external to the fpga and the latches/ffs, there are direct paths from latch/ff outputs to the i/o pads. this is done for each plc that is adjacent to a pic. the latches/ffs can be configured in three modes: 1. local synchronous set/reset: the input into the pfus lsr port is used to synchronously set or reset each latch/ff. 2. local asynchronous set/reset: the input into lsr asynchronously sets or resets each latch/ff. 3. latch/ff with front-end select: the data select signal (actually lsr) selects the input into the latches/ffs between the lut output and direct data in. for all three modes, each latch/ff can be indepen- dently programmed as either set or reset. each latch/ ff in the pfu is independently configured to operate as either a latch or flip-flop. figure 18 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. note: cd = configuration data. 5-2839(f).a figure 18. latch/ff set/reset configurations ce d s_set s_reset clk set reset q lsr gsrn cd ce d clk set reset lsr cd ce ce d clk set reset cd ce ce wd lsr gsrn pdinlr logic 0 wd f logic 0 wd gsrn q q pdintb f pdinlr pdintb f logic 0 wd pdinlr pdintb
lucent technologies inc. 17 data sheet june 1999 orca series 2 fpgas programmable logic cells (continued) plc routing resources generally, the orca foundry development system is used to automatically route interconnections. interac- tive routing with the orca foundry design editor (epic) is also available for design optimization. to use epic for interactive layout, an understanding of the routing resources is needed and is provided in this sec- tion. the routing resources consist of switching circuitry and metal interconnect segments. generally, the metal lines which carry the signals are designated as routing nodes (lines). the switching circuitry connects the rout- ing nodes, providing one or more of three basic func- tions: signal switching, amplification, and isolation. a net running from a pfu or pic output (source) to a plc or pic input (destination) consists of one or more lines, connected by switching circuitry designated as configurable interconnect points (cips). the following sections discuss plc, pic, and interquad routing resources. this section discusses the plc switching circuitry, intra-plc routing, inter-plc routing, and clock distribution. configurable interconnect points the process of connecting lines uses three basic types of switching circuits: two types of configurable intercon- nect points (cips) and bidirectional buffers (bidis). the basic element in cips is one or more pass transistors, each controlled by a configuration ram bit. the two types of cips are the mutually exclusive (or multi- plexed) cip and the independent cip. a mutually exclusive set of cips contains two or more cips, only one of which can be on at a time. an inde- pendent cip has no such restrictions and can be on independent of the state of other cips. figure 19 shows an example of both types of cips. f.13(f) figure 19. configurable interconnect point 3-statable bidirectional buffers bidirectional buffers provide isolation as well as amplifi- cation for signals routed a long distance. bidirectional buffers are also used to drive signals directly onto either vertical or horizontal xl and xh lines (to be described later in the inter-plc routing section). bidis are also used to indirectly route signals through the switching lines. any number from zero to eight bidis can be used in a given plc. the bidis in a plc are divided into two nibble-wide sets of four (bidi and bidih). each of these sets has a separate bidi controller that can have an application net connected to its tri input, which is used to 3-state enable the bidis. although only one application net can be connected to both bidi controllers, the sense of this signal (active-high, active-low, or ignored) can be con- figured independently. therefore, one set can be used for driving signals, the other set can be used to create 3-state buses, both sets can be used for 3-state buses, and so forth. 2 independent cip cd a b ab = multiplexed cip a b c a b c o o cd
18 lucent technologies inc. data sheet orca series 2 fpgas june 1999 programmable logic cells (continued) 5-4479p2(f) figure 20. 3-statable bidirectional buffers intra-plc routing the function of the intra-plc routing resources is to connect the pfus input and output ports to the routing resources used for entry to and exit from the plc. these are nets for providing pfu feedback, turning corners, or switching from one type of routing resource to another. pfu input and output ports. there are 19 input ports to each pfu. the pfu input ports are labeled a[4:0], b[4:0], wd[3:0], c0, ck, lsr, cin, and ce. the six output ports are o[4:0] and cout. these ports corre- spond to those described in the pfu section. switching lines. there are four sets of switching lines in each plc, one in each corner. each set consists of five switching elements, labeled sul[4:0], sur[4:0], sll[4:0], and slr[4:0], for the upper-left, upper-right, lower-left, and lower-right sections of the pfus, respectively. the switching lines connect to the pfu inputs and outputs as well as the bidi and bidih lines, to be described later. they also connect to both the horizontal and vertical x1 and x4 lines (inter-plc rout- ing resources, described below) in their specific corner. one of the four sets of switching lines can be con- nected to a set of switching lines in each of the four adjacent plcs or pics. this allows direct routing of up to five signals without using inter-plc routing. bidi/bidih lines. there are two sets of bidirectional lines in the plc, each set consisting of four bidirec- tional buffers. they are designated bidi and bidih and have similar functionality. the bidi lines are used in conjunction with the xl lines, and the bidih lines are used in conjunction with the xh lines. each side of the four bidis in the plc is connected to a bidi line on the left (bl[3:0]) and on the right (br[3:0]). these lines can be connected to the xl lines through cips, with bl[3:0] connected to the vertical xl lines and br[3:0] con- nected to the horizontal xl lines. both bl[3:0] and br[3:0] have cips which connect to the switching lines. similarly, each side of the four bidihs is connected to a bidih line: blh[3:0] on the left and brh[3:0] on the right. these lines can also be connected to the xh lines through cips, with blh[3:0] connected to the ver- tical xh lines and brh[3:0] connected to the horizontal xh lines. both blh[3:0] and brh[3:0] have cips which connect to the switching lines. cips are also provided to connect the bidih and bidil lines together on each side of the bidis. for example, blh3 can connect to bl3, while brh3 can connect to br3. right-left bidi left-right bidi unused bidi left-right bidi bidi controller tri right-left bidih left-right bidih unused bidih left-right bidih bidih controller
lucent technologies inc. 19 data sheet june 1999 orca series 2 fpgas programmable logic cells (continued) inter-plc routing resources the inter-plc routing is used to route signals between plcs. the lines occur in groups of four, and differ in the numbers of plcs spanned. the x1 lines span one plc, the x4 lines span four plcs, the xh lines span one-half the width (height) of the plc array, and the xl lines span the width (height) of the plc array. all types of lines run in both horizontal and vertical directions. table 5 shows the groups of inter-plc lines in each plc. in the table, there are two rows/columns each for x1 and x4 lines. in the design editor, the horizontal x1 and x4 lines are located above and below the pfu. similarly, the vertical segments are located on each side. the xl and xh lines only run below and to the left of the pfu. the indexes specify individual lines within a group. for example, the vx4[2] line runs vertically to the left of the pfu, spans four plcs, and is the third line in the 4-bit wide bus. table 5. inter-plc routing resources figure 21 shows the inter-plc routing within one plc. figure 22 provides a global view of inter-plc routing resources across multiple plcs. 5-4528(f) figure 21. single plc view of inter-plc lines x1 lines. there are a total of 16 x1 lines per plc: eight vertical and eight horizontal. each of these is sub- divided into nibble-wide buses: hx1[3:0], hx1[7:4], vx1[3:0], and vx1[7:4]. an x1 line is one plc long. if a net is longer than one plc, an x1 line can be lengthened to n times its length by turning on n C 1 cips. a signal is routed onto an x1 line via the switch- ing lines. x4 lines. there are four sets of four x4 lines, for a total of 16 x4 lines per plc. they are hx4[3:0], hx4[7:4], vx4[3:0], and vx4[7:4]. each set of x4 lines is twisted each time it passes through a plc, and one of the four is broken with a cip. this allows a signal to be routed for a length of four cells in any direction on a single line without additional cips. the x4 lines can be used to route any nets that require minimum delay. a longer net is routed by connecting two x4 lines together by a cip. the x4 lines are accessed via the switching lines. horizontal lines vertical lines distance spanned hx1[3:0] vx1[3:0] one plc hx1[7:4] vx1[7:4] one plc hx4[3:0] vx4[3:0] four plcs hx4[7:4] vx4[7:4] four plcs hxl[3:0] vxl[3:0] plc array hxh[3:0] vxh[3:0] 1/2 plc array ckl, ckr ckt, ckb plc array programmable function unit direct[4:0] hx4[7:4] hx1[7:4] direct[4:0] hxh[3:0] hx1[3:0] direct[4:0] direct[4:0] hx4[3:0] vx4[7:4] vx1[7:4] vxl[3:0] vx1[3:0] vx4[3:0] vxh[3:0] ckb, ckt hxl[3:0] ckl, ckr
20 lucent technologies inc. data sheet orca series 2 fpgas june 1999 programmable logic cells (continued) xl lines. the long xl lines run vertically and horizon- tally the height and width of the array, respectively. there are a total of eight xl lines per plc: four hori- zontal (hxl[3:0]) and four vertical (vxl[3:0]). each plc column has four xl lines, and each plc row has four xl lines. each of the xl lines connects to the two pics at either end. the series 2, which consists of a 18 x 18 array of plcs, contains 72 vxl and 72 hxl lines. they are intended primarily for global signals which must travel long distances and require minimum delay and/or skew, such as clocks. there are three methods for routing signals onto the xl lines. in each plc, there are two long-line drivers: one for a horizontal xl line, and one for a vertical xl line. using the long-line drivers produces the least delay. the xl lines can also be driven directly by pfu outputs using the bidi lines. in the third method, the xl lines are accessed by the bidirectional buffers, again using the bidi lines. xh lines . four by half (xh) lines run horizontally and four xh lines run vertically in each row and column in the array. these lines travel a distance of one-half the plc array before being broken in the middle of the array, where they connect to the interquad block (dis- cussed later). they also connect at the periphery of the fpga to the pics, like the xl lines. the xh lines do not twist like xl lines, allowing nibble-wide buses to be routed easily. two of the three methods of routing signals onto the xl lines can also be used for the xh lines. a special xh line driver is not supplied for the xh lines. clock lines. for a very fast and low-skew clock (or other global signal tree), clock lines run the entire height and width of the plc array. there are two hori- zontal clock lines per plc row (ckl, ckr) and two vertical clock lines per plc column (ckt, ckb). the source for these clock lines can be any of the four i/o buffers in the pic. the horizontal clock lines in a row (ckl, ckr) are driven by the left and right pics, respectively. the vertical clock lines in a column (ckt, ckb) are driven by the top and bottom pics, respec- tively. the clock lines are designed to be a clock spine. in each plc, there is a fast connection available from the clock line to the long-line driver (described earlier). with this connection, one of the clock lines in each plc can be used to drive one of the four xl lines perpendic- ular to it, which, in turn, creates a clock tree. this feature is discussed in detail in the clock distribu- tion network section. minimizing routing delay the cip is an active element used to connect two lines. as an active element, it adds significantly to the resis- tance and capacitance of a net, thus increasing the nets delay. the advantage of the x1 line over a x4 line is routing flexibility. a net from plc db to plc cb is eas- ily routed by using x1 lines. as more cips are added to a net, the delay increases. to increase speed, routes that are greater than two plcs away are routed on the x4 lines because a cip is located only in every fourth plc. a net that spans eight plcs requires seven x1 lines and six cips. using x4 lines, the same net uses two lines and one cip. all routing resources in the plc can carry 4-bit buses. in order for data to be used at a destination plc that is in data path mode, the data must arrive unscrambled. for example, in data path operation, the least signifi- cant bit 0 must arrive at either a[0] or b[0]. if the bus is to be routed by using either x4 or xl lines (both of which twist as they propagate), the bus must be placed on the appropriate lines at the source plc so that the data arrives at the destination unscrambled. the switching lines provide the most efficient means of con- necting adjacent plcs. signals routed with these lines have minimum propagation delay.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 21 programmable logic cells (continued) 5-2841(f)2c.r9 figure 22. multiple plc view of inter-plc routing pfu pfu pfu pfu pfu pfu pfu pfu pfu shows plcs ckr ckl ckr ckl hx4[4] hx4[5] hx4[6] hx4[7] hx1[7:4] hx4[5] hx4[6] hx4[7] hx4[4] hxl[0] hxl[1] hxl[2] hxl[3] hx1[3:0] hx4[0] hx4[1] hx4[2] hx4[3] hxl[3] hxl[0] hxl[1] hxl[2] hx4[1] hx4[2] hx4[3] hx4[0] hx4[4] hx4[5] hx4[6] hx4[7] hx1[7:4] hx4[5] hx4[6] hx4[7] hx4[4] hx1[7:4] hx4[4] hx4[5] hx4[6] hx4[7] hx4[5] hx4[6] hx4[7] hx4[4] hxl[0] hxl[1] hxl[2] hxl[3] hx4[0] hx4[1] hx4[2] hx4[3] hxl[3] hxl[0] hxl[1] hxl[2] hx4[1] hx4[2] hx4[3] hx4[0] ckr ckl hxh[3:0] hx1[7:4] hx1[3:0] ckr ckl hxh[3:0] hx1[7:4] hx1[3:0] ckr ckl hxh[3:0] hx1[7:4] hx1[3:0] ckr ckl hxh[3:0] vx1[3:0] ckt ckb vx4[0] vx4[1] vx4[2] vx4[3] vx4[4] vx4[5] vx4[6] vx4[7] vxh[3:0] vx1[7:4] vxl[0] vxl[1] vxl[2] vxl[3] vx4[1] vx4[2] vx4[3] vx4[0] vx4[5] vx4[6] vx4[7] vx4[4] vxl[1] vxl[2] vxl[3] vxl[0] vx4[0] vx4[1] vx4[2] vx4[3] vx1[3:0] ckt ckb vx4[1] vx4[2] vx4[3] vx4[0] vx4[0] vx4[1] vx4[2] vx4[3] vx4[4] vx4[5] vx4[6] vx4[7] vxl[0] vxl[1] vxl[2] vxl[3] vx4[1] vx4[2] vx4[3] vx4[0] vx4[5] vx4[6] vx4[7] vx4[4] vxl[3] vxl[0] vxl[1] vxl[2] vx1[3:0] ckt ckb vx1[3:0] ckt ckb vxh[3:0] vx1[7:4] vx1[3:0] ckt ckb vxh[3:0] vx1[7:4] vx1[3:0] ckt ckb vxh[3:0] vx1[7:4]
22 lucent technologies inc. data sheet orca series 2 fpgas june 1999 programmable logic cells (continued) plc architectural description figure 23 is an architectural drawing of the plc which reflects the pfu, the lines, and the cips. a discussion of each of the letters in the drawing follows. a . these are switching lines which give the router flexi- bility. in general switching theory, the more levels of indirection there are in the routing, the more routable the network is. the switching lines can also connect to adjacent plcs. the switching lines provide direct connections to plcs directly to the top, bottom, left, and right, with- out using other routing resources. the ability to dis- able this connection between plcs is provided so that each side of these connections can be used exclusively as switching lines in their respective plc. b . these cips connect the x1 routing. these are located in the middle of the plc to allow the block to connect to either the left end of the horizontal x1 line from the right or the right end of the horizontal x1 line from the left, or both. by symmetry, the same principle is used in the vertical direction. the x1 lines are not twisted, making them suitable for data paths. c . this set of cips is used to connect the x1 and x4 nets to the switching lines or to other x1 and x4 nets. the cips on the major diagonal allow data to be transmitted from x1 nets to the switching lines without being scrambled. the cips on the major diagonal also allow unscrambled data to be passed between the x1 and x4 nets. in addition to the major diagonal cips for the x1 lines, other cips provide an alternative entry path into the plc in case the first one is already used. the other cips are arrayed in two patterns, as shown. both of these patterns start with the main diagonal, but the extra cips are arrayed on either a parallel diagonal shifted by one or shifted by two (modulo the size of the vertical bus (5)). this allows any four application nets incident to the plc corner to be transferred to the five switching lines in that corner. many patterns of five nets can also be trans- ferred. d . the x4 lines are twisted at each plc. one of the four x4 lines is broken with a cip, which allows a sig- nal to be routed a distance of four plcs in any direc- tion on a single line without an intermediate cip. the x4 lines are less populated with cips than the x1 lines to increase their speed. a cip can be enabled to extend an x4 line four more plcs, and so on. for example, if an application signal is routed onto hx4[4] in a plc, it appears on hx4[5] in the plc to the right. this signal step-up continues until it reaches hx4[7], two plcs later. at this point, the user can break the connection or continue the signal for another four plcs. e . these symbols are bidirectional buffers (bidis). there are four bidis per plc, and they provide sig- nal amplification as needed to decrease signal delay. the bidis are also used to transmit signals on xl lines. f . these are the bidi and bidih controllers. the 3- state control signal can be disabled. they can be configured as active-high or active-low indepen- dently of each other. g . this set of cips allows a bidi to get or put a signal from one set of switching lines on each side. the bidis can be accessed by the switching lines. these cips allow a nibble of data to be routed though the bidis and continue to a subsequent block. they also provide an alternative routing resource to improve routability. h . these cips are used to take data from/to the bidis to/from the xl lines. these cips have been opti- mized to allow the bidi buffers to drive the large load usually seen when using xl lines. i . each latch/ff can accept data: from an lut output; from a direct data input signal from general routing; or, as in the case of plcs located in the two rows (columns) adjacent to pics, directly from the pad. in addition, the lut outputs can bypass the latches/ ffs completely and output data on the general rout- ing resources. the four inputs shown are used as the direct input to the latches/ffs from general rout- ing resources. if the lut is in memory mode, the four inputs wd[3:0] are the data input to the mem- ory.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 23 programmable logic cells (continued) 5-4479(f).r2 figure 23. plc architecture pfu:r1c2 hx4[7] hx4[6] hx4[5] hx4[4] hx1[7] hx1[6] hx1[5] hx1[4] inl[4] inl[3] inl[2] inl[1] inl[0] vx4[7] vx4[6] vx4[5] vx4[4] vx1[7] vx1[6] vx1[5] vx1[4] vxl[3] vxl[2] vxl[1] vxl[0] carry_t ckl ckr carry_l vxh[3] vxh[2] vxh[1] vxh[0] vx4[4] vx4[7] vx4[6] vx4[5] vx1[7] vx1[6] vx1[5] vx1[4] vxl[0] vxl[3] vxl[2] vxl[1] hxl[3] hxl[2] hxl[1] hxl[0] hx4[3] hx4[2] hx4[1] hx4[0] hx1[3] hx1[2] hx1[1] hx1[0] carry_b hxh[3] hxh[2] hxh[1] hxh[0] vxh[3] vxh[2] vxh[1] vxh[0] hxl[0] hxl[3] hxl[2] hxl[1] hx4[2] hx4[1] hx4[0] hx4[3] hx1[3] hx1[2] hx1[1] hx1[0] vx1[3] vx1[2] vx1[1] vx1[0] vx4[0] vx4[3] vx4[2] vx4[1] inb[4] inb[3] inb[2] inb[0] inb[1] hxh[3] hxh[2] hxh[1] hxh[0] gsrn ckb ckt int[4] int[3] int[2] int[1] int[0] hx4[6] hx4[5] hx4[4] hx4[7] hx1[7] hx1[6] hx1[5] hx1[4] inr[4] inr[3] inr[2] inr[1] inr[0] ckl ckr carry_r gsrn vx1[3] vx1[2] vx1[1] vx1[0] vx4[3] vx4[2] vx4[1] vx4[0] ckb ckt hck vck lsr ce cout cin j n ck gsrn a[4] a[3] a[2] a[1] a[0] b[4] b[3] b[2] b[1] b[0] c0 wd[3] wd[2] wd[1] wd[0] o[2] o[0] o[4] i o[3] o[1] see figure 14 c cb l d b a d c b a aa a a q h l c c a k n f m db c m d a t t s u u t t l s r p q r o g e o u w u v c c g h l
24 lucent technologies inc. data sheet orca series 2 fpgas june 1999 programmable logic cells (continued) j . any five of the eight output signals can be routed out of the plc. the eight signals are the four lut out- puts (f0, f1, f2, and f3) and the four latch/ff out- puts (q0, q1, q2, and q3). this allows the user to access all four latch/ff outputs, read the present state and next state of a latch/ff, build a 4-bit shift register, etc. each of the outputs can drive any num- ber of the five pfu outputs. the speed of a signal can be increased by dividing its load among multiple pfu output drivers. k . these lines deliver the auxiliary signals clock enable and set/reset to the latches/ffs. all four of the latches/ffs share these signals. l . this is the clock input to the latches/ffs. any of the horizontal and vertical xh or xl lines can drive the clock of the plc latches/ffs. long-line drivers are provided so that a plc can drive one xl line in the horizontal direction and one xl line in the vertical direction. the xl lines in each direction exhibit the same properties as x4 lines, except there are no cips. the clock lines (ckl, ckr, ckt, and ckb) and multiplexers/drivers are used to connect to the xl lines for low-skew, low-delay global signals. the long lines run the length or width of the plc array. they rotate to allow four plcs in one row or column to generate four independent global signals. these lines do not have to be used for clock routing. any highly used application net can use this resource, especially one requiring low skew. m . these lines are used to route the fast carry signal to/ from the neighboring four plcs. the carry-out (cout) of the pfu can also be routed out of the pfu onto the fifth output (o4). the carry-in (cin) signal can also be supplied by the b4 input to the pfu. n . these are the 11 logic inputs to the lut. the a[4:0] inputs are provided into hluta, and the b[4:0] inputs are provided into hlutb. the c0 input bypasses the main lut and is used in the pfumux, pfuxor, and pfunand functions (f5m, f5x modes). since this input bypasses the lut, it can be used as a fast path around the lut, allowing the implemen- tation of fast, wide combinatorial functions. the c0 input can be disabled or inverted. o . the xh lines run one-half the length (width) of the array before being broken by a cip. p . the bidihs are used to access the xh lines. q . the bidih lines are used to connect the bidihs to the xsw lines, the xh lines, or the bidi lines. r . these cips connect the bidi lines and the bidih lines. s . these are clock lines (ckt, ckb, ckl, and ckr) with the multiplexers and drivers to connect to the xl lines. t . these cips connect x1 lines which cross in each corner to allow turns on the x1 lines without using the xsw lines. u . these cips connect x4 lines and xsw lines, allowing nets that run a distance that is not divisible by four to be routed more efficiently. v . this routing structure allows any pfu output, includ- ing lut and latch/ff outputs, to be placed on o4 and be routed onto the fast carry routing. w . this routing structure allows the fast carry routing to be routed onto the c0 pfu input.
lucent technologies inc. 25 data sheet june 1999 orca series 2 fpgas programmable input/output cells the programmable input/output cells (pics) are located along the perimeter of the device. each pic interfaces to four bond pads and contains the neces- sary routing resources to provide an interface between i/o pads and the plcs. each pic is composed of input buffers, output buffers, and routing resources as described below. table 6 provides an overview of the programmable functions in an i/o cell. a is a simplified diagram of the functionality of the or2cxxa series i/o cells, while b is a simplified functional diagram of the or2txxa and or2txxb series i/o cells. table 6. input/output cell options inputs each i/o can be configured to be either an input, an output, or bidirectional i/o. inputs for the or2cxxa can be configured as either ttl or cmos compatible. the i/o for the or2txxa and or2txxb series devices are 5 v tolerant, and will be described in a later section of this data sheet. pull-up or pull-down resistors are avail- able on inputs to minimize power consumption. to allow zero hold time to plc latches/ffs, the input signal can be delayed. when enabled, this delay affects the input signal driven to general routing, but does not affect the clock input or the input lines that drive the tridi buffers (used to drive onto xl, xh, bidi, and bidih lines). a fast path from the input buffer to the clock lines is also provided. any one of the four i/o pads on any pic can be used to drive the clock line generated in that pic. this path cannot be delayed. to reduce the time required to input a signal into the fpga, a dedicated path (pdin) from the i/o pads to the pfu flip-flops is provided. like general input sig- nals, this signal can be configured as normal or delayed. the delayed direct input can be selected inde- pendently from the delayed general input. inputs should have transition times of less than 500 ns and should not be left floating. if an input can float, a pull-up or pull-down should be enabled. floating inputs increase power consumption, produce oscillations, and increase system noise. the or2cxxa inputs have a typical hysteresis of approximately 280 mv (200 mv for the or2txxa and or2txxb) to reduce sensitivity to input noise. the pic contains input circuitry which pro- vides protection against latch-up and electrostatic dis- charge. input option input levels ttl/cmos (or2cxxa only) 5 v pci compliant (or2cxxa only) 3.3 v pci compliant (or2txxa only) 3.3 v and 5 v pci compliant (or2txxb only) input speed fast/delayed float value pull-up/pull-down/none direct-in to ff fast/delayed output option output drive 12 ma/6 ma or 6 ma/3 ma output speed fast/slewlim/sinklim output source ff direct-out/general routing output sense active-high/-low 3-state sense active-high/-low (3-state)
26 lucent technologies inc. data sheet orca series 2 fpgas june 1999 programmable input/output cells (continued) a. simplified diagram of or2cxxa programmable i/o cell (pic) b. simplified diagram of or2txxa/or2txxb programmable i/o cell (pic) figure 24. simplified diagrams outputs the pics output drivers have programmable drive capability and slew rates. three propagation delays (fast, slewlim, sinklim) are available on output drivers. the sinklim mode has the longest propagation delay and is used to minimize system noise and minimize power consumption. the fast and slewlim modes allow critical timing to be met. the drive current is 12 ma sink/6 ma source for the slewlim and fast output speed selections and 6 ma sink/3 ma source for the sinklim output. two adja- cent outputs can be interconnected to increase the out- put sink current to 24 ma. all outputs that are not speed critical should be config- ured as sinklim to minimize power and noise. the num- ber of outputs that switch simultaneously in the same direction should be limited to minimize ground bounce. to minimize ground bounce problems, locate heavily loaded output buffers near the ground pads. ground bounce is generally a function of the driving circuits, traces on the pcb, and loads and is best determined with a circuit simulation. outputs can be inverted, and 3-state control signals can be active-high or active-low. an open-drain output may be obtained by using the same signal for driving the output and 3-state signal nets so that the buffer out- put is enabled only by a low. at powerup, the output drivers are in slewlim mode, and the input buffers are configured as ttl-level compatible with a pull-up. if an output is not to be driven in the selected configuration mode, it is 3-stated. 5 v tolerant i/o (or2txxa) the i/o on the or2txxa series devices allow intercon- nection to both 3.3 v and 5 v device (selectable on a per-pin basis) by way of special v dd 5 pins that have been added to the or2txxa devices. if any i/o on the or2txxa device interfaces to a 5 v input, then all of the v dd 5 pins must be connected to the 5 v supply. if no pins on the device interface to a 5 v signal, then the v dd 5 pins must be connected to the 3.3 v supply. if the v dd 5 pins are disconnected (i.e., they are float- ing), the device will not be damaged; however, the device may not operate properly until v dd 5 is returned to a proper voltage level. if the v dd 5 pins are then shorted to ground, a large current flow will develop, and the device may be damaged. pull-up v dd delay ttl/cmos pa d slew rate polarity dout/out pull-down dintb, dinlr in polarity tri 5-4591(f) pull-up v dd delay pa d slew rate polarity dout/out pull-down dintb, dinlr in polarity tri 5-4591.t(f)
lucent technologies inc. 27 data sheet june 1999 orca series 2 fpgas programmable input/output cells (continued) regardless of the power supply that the v dd 5 pins are connected to (5 v or 3.3 v), the or2txxa devices will drive the pin to the 3.3 v levels when the output buffer is enabled. if the other device being driven by the or2txxa device has ttl-compatible inputs, then the device will not dissipate much input buffer power. this is because the or2txxa output is being driven to a higher level than the ttl level required. if the other device has a cmos-compatible input, the amount of input buffer power will also be small. both of these power values are dependent upon the input buffer char- acteristics of the other device when driven at the or2txxa output buffer voltage levels. the 2txxa device has internal programmable pull-ups on the i/o buffers. these pull-up voltages are always referenced to v dd . this means that the v dd 5 voltage has no effect on the value of the pull-up voltage at the pad. this voltage level is always sufficient to pull the input buffer of the 2txxa device to a high state. the pin on the 2txxa device will be at a level 1.0 v below v dd (minimum of 2.0 v with a minimum v dd of 3.0 v). this voltage is sufficient to pull the external pin up to a 3.3 v cmos high-input level (1.8 v min) or a ttl high-input level (2.0 v min) in a 5 v tolerant system, but it will never pull the pad up to the v dd 5 rail. therefore, in a 5 v tolerant system using 5 v cmos parts, care must be taken to evaluate the use of these pull-ups to pull the pin of the 2txxa device to a typical 5 v cmos high-input level (2.2 v min). for more information on 5 v tolerant i/os, please see orca ? series 5 v tolerant i/os application note (ap99-027fpga), may 1999. 5 v tolerant i/o (or2txxb) the i/o on the or2txxb series devices allow intercon- nection to both 3.3 v and 5 v device (selectable on a per-pin basis). unlike the or2txxa family, when inter- faceing into a 5 v signal, it no longer requires a v dd 5 supply. the or2txxb devices will drive the pin to the 3.3 v lev- els when the output buffer is enabled. if the other device being driven by the or2txxb device has ttl- compatible inputs, then the device will not dissipate much input buffer power. this is because the or2txxb output is being driven to a higher level than the ttl level required. if the other device has a cmos-compat- ible input, the amount of input buffer power will also be small. both of these power values are dependent upon the input buffer characteristics of the other device when driven at the or2txxb output buffer voltage levels. the or2txxb device has internal programmable pull- ups on the i/o buffers. these pull-up voltages are always referenced to v dd and are always sufficient to pull the input buffer of the or2txxb device to a high state. the pin on the or2txxb device will be at a level 1.0 v below v dd (minimum of 2.0 v with a minimum v dd of 3.0 v). this voltage is sufficient to pull the exter- nal pin up to a 3.3 v cmos high-input level (1.8 v, min) or a ttl high input level (2.0 v, min) in a 5 v tolerant system. therefore, in a 5 v tolerant system using 5 v cmos parts, care must be taken to evaluate the use of these pull-ups to pull the pin of the or2txxb device to a typical 5 v cmos high-input level (2.2 v, min). pci compliant i/o the i/o on the or2txxb series devices allows compli- ance with pci local bus (rev. 2.1) 5 v and 3.3 v signal- ing environments. the signaling environment used for each input buffer can be selected on a per-pin basis. the selection provides the appropriate i/o clamping diodes for pci compliance. or2txxb devices have 5 v tolerant i/os as previously explained, but can optionally be selected on a pin-by- pin basis to be pci bus 3.3 v signaling compliant (pci bus 5 v signaling compliance occurs in 5 v tolerant operation mode). inputs may have a pull-up or pull- down resistor selected on an input for signal stabiliza- tion and power management. input signals in a pio can be passed to pic routing on any of three paths, two general signal paths into pic routing, and/or a fast route into the clock routing system. or2txxa series devices are only compliant in 3.3 v pci local bus (rev 2.1) signalling environments. or2cxxa devices are only compliant in 5 v pci local bus (rev 2.1) signalling environments.
28 lucent technologies inc. data sheet orca series 2 fpgas june 1999 programmable input/output cells (continued) pic routing resources the pic routing is designed to route 4-bit wide buses efficiently. for example, any four consecutive i/o pads can have both their input and output signals routed into one plc. using only pic routing, either the input or output data can be routed to/from a single plc from/to any eight pads in a row, as in figure 25. the connections between plcs and the i/o pad are provided by two basic types of routing resources. these are routing resources internal to the pic and routing resources used for pic-plc connection. figure 26 and figure 27 show a high-level and detailed view of these routing resources, respectively. 5-4504(f) figure 25. simplified pic routing diagram the pics name is represented by a two-letter designa- tion to indicate on which side of the device it is located followed by a number to indicate in which row or col- umn it is located. the first letter, p, designates that the cell is a pic and not a plc. the second letter indicates the side of the array where the pic is located. the four sides are left (l), right (r), top (t), and bottom (b). the individual i/o pad is indicated by a single letter (either a, b, c, or d) placed at the end of the pic name. as an example, pl10a indicates a pad located on the left side of the array in the tenth row. each pic has four pads and each pad can be config- ured as an input, an output (3-statable), a direct output, or a bidirectional i/o. when the pads are used as inputs, the external signals are provided to the internal circuitry at in[3:0]. when the pads are used to provide direct inputs to the latches/ffs, they are connected through din[3:0]. when the pads are used as outputs, the internal signals connect to the pads through out[3:0]. when the pads are used as direct outputs, the output from the latches/flip-flops in the plcs to the pic is designated dout[3:0]. when the outputs are 3-statable, the 3-state enable signals are ts[3:0]. routing resources internal to the pic for inter-pic routing, the pic contains 14 lines used to route signals around the perimeter of the fpga. figure 25 shows these lines running vertically for a pic located on the left side. figure 26 shows the lines run- ning horizontally for a pic located at the top of the fpga. pxl lines. each pic has two pxl lines, labeled pxl[1:0]. like the xl lines of the plc, the pxl lines span the entire edge of the fpga. pxh lines. each pic has four pxh lines, labeled pxh[3:0]. like the xh lines of the plc, the pxh lines span half the edge of the fpga. px2 lines. there are four px2 lines in each pic, labeled px2[3:0]. the px2 lines pass through two adja- cent pics before being broken. these are used to route nets around the perimeter equally a distance of two or more pics. px1 lines. each pic has four px1 lines, labeled px1[3:0]. the px1 lines are one pic long and are extended to adjacent pics by enabling cips. pad d i/o3 4 pxl 2 ck 2 pic switching matrix pad c i/o2 4 pad b i/o1 4 pad a i/o0 4 pxh 4 px2 4 px1 4 plc x4 4 plc x1 4 plc psw 5 plc dout 4 plc xl 4 plc xh 4 plc x1 4 plc x4 4 plc din 4 pxl 2 pxh 4 px2 4 px1 4
lucent technologies inc. 29 data sheet june 1999 orca series 2 fpgas programmable input/output cells (continued) pic architectural description the pic architecture given in figure 26 is described using the following letter references. the figure depicts a pic at the top of the array, so inter-pic routing is hor- izontal and the indirect pic-plc routing is horizontal to vertical. in some cases, letters are provided in more than one location to indicate the path of a line. a . as in the plcs, the pic contains a set of lines which run the length (width) of the array. the pxl lines connect in the corners of the array to other pxl lines. the pxl lines also connect to the pic bidi, pic bidih, and lldrv lines. as in the plc xl lines, the pxh lines twist as they propagate through the pics. b . as in the plcs, the pic contains a set of lines which run one-half the length (width) of the array. the pxh lines connect in the corners and in the middle of the array perimeter to other pxh lines. the pxh lines also connect to the pic bidi, pic bidih, and lldrv lines. as in the plc xh lines, the pxh lines do not twist as they propagate through the pics. c . the px2[3:0] lines span a length of two pics before intersecting with a cip. the cip allows the length of a path using px2 lines to be extended two pics. d . the px1[3:0] lines span a single pic before inter- secting with a cip. the cip allows the length of a path using px1 lines to be extended by one pic. e . these are four dedicated direct output lines con- nected to the output buffers. the dout[3:0] signals go directly from a plc latch/ff to an output buffer, minimizing the latch/ff to pad propagation delay. f . this is a direct path from the input pad to the plc latch/flip-flops in the two rows (columns) adjacent to pics. this input allows a reduced setup time. direct inputs from the top and bottom pic rows are pdintb[3:0]. direct inputs from the left and right pic columns are pdinlr[3:0]. g . the out[3:0], ts[3:0], and in[3:0] signals for each i/o pad can be routed directly to the adjacent plcs switching lines. h . the four tridi buffers allow connections from the pads to the plc xl lines. the tridis also allow connections between the plc xl lines and the pbidi lines, which are described in j below. i . the four tridih buffers allow connections from the pads to the plc xh lines. the tridihs also allow connections between the plc xh lines and the pbidih lines, which are described in k below. j . the pbidi lines (bidi[3:0]) connect the pxl lines, pxh lines, and the px1 lines. these are bidirec- tional in that the path can be from the pxl, pxh, or px1 lines to the xl lines, or from the xl lines to the pxl, pxh, or px1 lines. k . the pbidih lines (bidih[3:0]) connect the pxl lines, pxh lines, and the px1 lines. these are bidi- rectional in that the path can be from the pxl, pxh, or px1 lines to the xh lines, or from the xh lines to the pxl, pxh, or px1 lines. l . the llin[3:0] lines provide a fast connection from the i/o pads to the xl and xh lines. m .this set of cips allows the eight x1 lines (four on each side) of the plc perpendicular to the pic to be connected to either the px1 or px2 lines in the pic. n . this set of cips allows the eight x4 lines (four on each side) of the plc perpendicular to the pic to be connected to the px1 lines. this allows fast access to/from the i/o pads from/to the plcs. o . all four of the plc x4 lines in a group connect to all four of the plc x4 lines in the adjacent plc through a cip. (this differs from the orca 1c series in which two of the x4 lines in adjacent plcs are directly connected without any cips.) p . the long-line driver (lldrv) line can be driven by the xsw4 switching line of the adjacent plc. to pro- vide connectivity to the pads, the lldrv line can also connect to any of the four pxh or to one of the pxl lines. the 3-state enable (ts[i]) for all four i/o pads can be driven by xsw4, pxh, or pxl lines. q . for fast clock routing, one of the four i/o pads in each pic can be selected to be driven onto a dedi- cated clock line. the clock line spans the length (width) of the plc array. this dedicated clock line is typically used as a clock spine. in the plcs, the spine is connected to an xl line to provide a clock branch in the perpendicular direction. since there is another clock line in the pic on the opposite side of the array, only one of the i/o pads in a given row (column) can be used to generate a global signal in this manner, if all plcs are driven by the signal.
data sheet orca series 2 fpgas june 1999 30 lucent technologies inc. programmable input/output cells (continued) 5-2843(f).r8 figure 26. pic architecture dt dt dt dt pa pb pc pd pxl[1] pxl[0] px2[2] px2[3] px2[0] px2[1] px1[0] px1[1] px1[2] px1[3] pxh[1] pxh[2] pxh[3] pxh[0] b a c d fe g q pxl[0] pxl[1] px2[0] px2[1] px2[2] px2[3] px1[0] px1[1] px1[2] px1[3] pxh[1] pxh[2] pxh[3] pxh[0] b a c d ts0 out0 in0 dout0 ts1 out1 in1 dout1 ts3 out3 in3 dout3 ts2 out2 in2 dout2 pic detail bidi3 f o n o lldrv m i l j k n d c p q m bidih3 bidih2 bidih1 bidih0 bidi2 bidi1 bidi0 llin3 llin2 llin1 llin0 p p vxl[3] vxl[2] vxl[1] vxl[0] vx1[7] vx1[6] vx1[5] vx1[4] vx1[3] vx1[2] vx1[1] vx1[0] dout[3] dout[2] dout[1] xsw[3] xsw[2] xsw[1] xsw[0] xsw[4] dout[0] ckt vxh[3] vxh[2] vxh[1] vxh[0] vx4[7] vx4[6] vx4[5] vx4[4] pdintb[3] pdintb[2] pdintb[1] pdintb[0] vx4[3] vx4[2] vx4[1] vx4[0] plc-pic routing resources there is no direct connection between the inter-pic lines and the plc lines. all connections to/from the plc must be done through the connecting lines which are perpendicular to the lines in the pic. the use of perpendicular and parallel lines will be clearer if the plc and pic architectures (figure 23 and figure 26) are placed side by side. twenty-nine lines in the plc can be connected to the 15 lines in the pic. multiple connections between the pic px1 lines and the plc x1 lines are available. these allow buses placed in any arbitrary order on the i/o pads to be unscrambled when placed on the plc x1 lines. con- nections are also available between the pic px2 lines and the plc x1 lines. there are eight tridirectional (four tridi/four tridih) buffers in each pic; they can do the following: n drive a signal from an i/o pad onto one of the adja- cent plcs xl or xh lines n drive a signal from an i/o pad onto one of the two pxl or four pxh lines in the pic n drive a signal from the plc xl or xh lines onto one of the two pxl or four pxh lines in the pic n drive a signal from the pic pxl or pxh lines onto one of the plc xl or xh lines
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 31 programmable input/output cells (continued) figure 27 shows paths to and from pads and the use of mux cips to connect lines. detail a shows six mux cips for the pad p0 used to construct the net for the 3-state signal. in the mux cip, one of six lines is connected to a line to form the net. in this case, the ts0 signal can be driven by either of the two pxls, px1[0], px1[1], xsw[0], or the lldrv lines. detail b shows the four mux cips used to drive the p1 output. the source line for out1 is either xsw[1], px1[1], px1[3], or px2[2]. 5-2843.bl(f).2c.r3 figure 27. pic detail dt dt dt dt pa pb pc pd ts0 out0 in0 dout0 ts1 out1 in1 dout1 ts3 out3 in3 dout3 ts2 out2 in2 dout2 pxl[1] pxl[0] px2[2] px2[3] px2[0] px2[1] px1[0] px1[1] px1[2] px1[3] pxh[1] pxh[2] pxh[3] pxh[0] pxl[1] pxl[0] px2[2] px2[3] px2[0] px2[1] px1[0] px1[1] px1[2] px1[3] pxh[1] pxh[2] pxh[3] pxh[0] dout[0] dout[1] dout[2] dout[3] xsw[0] xsw[1] xsw[2] xsw[3] lldrv a b
data sheet orca series 2 fpgas june 1999 32 lucent technologies inc. interquad routing in all the orca series 2 devices, the plc array is split into four equal quadrants. in between these quadrants, routing has been added to route signals between the quadrants, especially to the quadrant in the opposite corner. the two types of interquad blocks, vertical and horizontal, are pitch matched to pics. vertical inter- quad blocks (viq) run between quadrants on the left and right, while horizontal interquad blocks (hiq) run between top and bottom quadrants. since hiq and viq blocks have the same logic, only the hiq block is described below. the interquad routing connects xl and xh lines. it does not affect local routing (xsw, x1, x4, fast carry), so local routing is the same, whether plc-plc con- nections cross quadrants or not. there are no connec- tions to the local lines in the interquad blocks. figure 28 presents a (not to scale) view of interquad routing. figure 28. interquad routing 5-4538(f) viq0[4:0] viq1[4:0] viq2[4:0] viq3[4:0] 5 5 5 5 tmid bmid hiq3[4:0] hiq2[4:0] hiq1[4:0] hiq0[4:0] 5 5 5 5 see detail in figure 29 rmid lmid
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 33 interquad routing (continued) in the hiq block in figure 29, the xh lines from one quadrant connect through a cip to its counterpart in the opposite quadrant, creating a path that spans the plc array. since a passive cip is used to connect the two xh lines, a 3-state signal can be routed on the two xh lines in the opposite quadrants, and then they can be connected through this cip. in the hiq block, the 20 hiq lines span the array in a horizontal direction. the 20 hiq lines consist of four groups of five lines each. to effectively route nibble- wide buses, each of these sets of five lines can connect to only one of the bits of the nibble for both the xh and xl. for example, hiq0 lines can only connect to the xh0 and xl0 lines, and the hiq1 lines can connect only to the xh1 and xl1 lines, etc. buffers are provided for routing signals from the xh and xl lines onto the hiq lines and from the hiq lines onto the xh and xl lines. therefore, a connection from one quadrant to another can be made using only two xh lines (one in each quadrant) and one interquad line. 5-4537(f).r3 figure 29. hiq block detail hiq3[4] hiq3[3] hiq3[2] hiq3[1] hiq3[0] hiq2[4] hiq2[3] hiq2[2] hiq2[1] hiq2[0] hiq1[4] hiq1[3] hiq1[2] hiq1[1] hiq1[0] hiq0[4] hiq0[3] hiq0[2] hiq0[1] hiq0[0] vxh[3] vxh[2] vxh[1] vxh[0] vxl[3] vxl[2] vxl[1] vxl[0] vx4[7] vx4[6] vx4[5] vx4[4] vx1[7] vx1[6] vx1[5] vx1[4] vx4[7] vx4[6] vx4[5] vx4[4] vx1[7] vx1[6] vx1[5] vx1[4] vxh[3] vxh[2] vxh[1] vxh[0] vxl[3] vxl[2] vxl[1] vxl[0] hiq3[4] hiq3[3] hiq3[2] hiq3[1] hiq3[0] hiq2[4] hiq2[3] hiq2[2] hiq2[1] hiq2[0] hiq1[4] hiq1[3] hiq1[2] hiq1[1] hiq1[0] hiq0[4] hiq0[3] hiq0[2] hiq0[1] hiq0[0] carry carry vx4[3] vx4[2] vx4[1] vx4[0] vx1[3] vx1[2] vx1[1] vx1[0] vx1[3] vx1[2] vx1[1] vx1[0] vx4[3] vx4[2] vx4[1] vx4[0] int[4] int[3] int[2] int[1] int[0] gsrn ckb ckt inb[4] inb[3] inb[2] inb[1] inb[0] gsrn ckb ckt
data sheet orca series 2 fpgas june 1999 34 lucent technologies inc. interquad routing (continued) subquad routing (or2c40a/or2t40a only) in the orca or2c40a/or2t40a/or2t40b, each quadrant of the device is split into smaller arrays of plcs called subquads. each of these subquads is made of a 4 x 4 array of plcs (for a total of 16 per sub- quadrant), except at the outer edges of array, which have less than 16 plcs per subquad. new routing resources, called subquad lines, have been added between each adjacent pair of subquads to enhance the routability of the device. a portion of the center of the or2c40a and or2t40a array is shown in figure 30, including the subquad blocks containing a 4 x 4 array of plcs, the interquad routing lines, and the sub- quad routing lines. all of the inter-plc routing resources discussed previ- ously continue to be routed between a plc and its adjacent plc, even if the two adjacent plcs are in dif- ferent subquad blocks. since the plc routing has not been modified for the or2c40a/or2t40a architec- tures, this means that all of the same routing connec- tions are possible for these devices as for any other orca 2c series device. in this way, both the or2c40a and or2t40a/or2t40b are upwardly com- patible when compared with the att2cxx series devices. as the inter-plc routing runs between sub- quad blocks, it crosses the new subquad lines. when this happens, cips are used to connect the subquad lines to the x4 and/or the xh lines which lie along the other axis of the plc array. 5-4200(f).r5 figure 30. subquad blocks and subquad routing subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) subquad (4 x 4 plcs) see detail in figures 25 and 26 horizontal interquad routing (hiq) horizontal subquad routing (hsub) vertical subquad routing (vsub) vertical interquad routing (viq)
lucent technologies inc. 35 data sheet june 1999 orca series 2 fpgas interquad routing (continued) 5-4201(f).r4 figure 31. horizontal subquad routing connectivity the x4 and xh lines make the only connections to the subquad lines; therefore, the array remains symmetri- cal and homogeneous. since each subquad is made from a 4 x 4 array of plcs, the distance between sets of subquad lines is four plcs, which is also the dis- tance between the breaks of the x4 lines. therefore, each x4 line will cross exactly one set of subquad lines. since all x4 lines make the same connections to the subquad lines that they cross, all x4 lines in the array have the same connectivity, and the symmetry of the routing is preserved. since all xh lines cross the same number of subquad blocks, the symmetry is maintained for the xh lines as well. the new subquad lines travel a length of eight plcs (seven plcs on the outside edge) before they are bro- ken. unlike other inter-plc lines, they cannot be con- nected end-to-end. as shown in figure 30, some of the horizontal (vertical) subquad lines have connectivity to the subquad to the left of (above) the current subquad, while others have connectivity to the subquad to the right (below). this allows connections to/from the cur- rent subquad from/to the plcs in all subquads that sur- round it. between all subquads, including in the center of the array, there are three groups of subquad lines where each group contains four lines. figure 31 shows the connectivity of these three groups of subquad lines (hsub) to the vx4 and vxh lines running between a vertical pair of plcs. between each vertical pair of subquad blocks, four of the blocks shown in figure 31 are used, one for each pair of vertical plcs. the first two groups, depicted as a and b, have con- nectivity to only one of the two sets of x4 lines between pairs of plcs. since they are very lightly loaded, they are very fast. the third group, c, connects to both groups of x4 lines between pairs of plcs, as well as all of the xh lines between pairs of plcs, providing high flexibility. the connectivity for the vertical subquad rout- ing (vsub) is the same as described above for the hori- zontal subquad routing, when rotated onto the other axis. at the center row and column of each quadrant, a fourth group of subquad lines has been added. these subquad lines only have connectivity to the xh lines. the xh lines are also broken at this point, which means that each xh line travels one-half of the quad- rant (i.e., one-quarter of the device) before it is broken by a cip. since the xh lines can be connected end-to- end, the resulting line can be either one-quarter, one- half, three-quarters, or the entire length of the array. the connectivity of the xh lines and this fourth group of subquad lines, indicated as d, are detailed in figure 32. again, the connectivity for the vertical subquad routing (vsub) is the same as the horizontal subquad routing, when rotated onto the other axis. 5-4202(f).r3 figure 32. horizontal subquad routing connectivity (half quad) a c b hsub[11] hsub[10] hsub[9] hsub[8] hsub[7] hsub[6] hsub[5] hsub[4] hsub[3] hsub[2] hsub[1] hsub[0] hsub[11] hsub[10] hsub[9] hsub[8] hsub[7] hsub[6] hsub[5] hsub[4] hsub[3] hsub[2] hsub[1] hsub[0] vx4[7] vx4[6] vx4[5] vx4[4] vx4[3] vx4[2] vx4[1] vx4[0] vx4[3] vx4[2] vx4[1] vx4[0] vx4[7] vx4[6] vx4[5] vx4[4] vx4[3] vx4[2] vx4[1] vx4[0] vx4[3] vx4[2] vx4[1] vx4[0] a d b hsub[11] hsub[10] hsub[9] hsub[8] hsub[15] hsub[14] hsub[13] hsub[12] hsub[3] hsub[2] hsub[1] hsub[0] hsub[11] hsub[10] hsub[9] hsub[8] hsub[15] hsub[14] hsub[13] hsub[12] hsub[3] hsub[2] hsub[1] hsub[0] vx4[7] vx4[6] vx4[5] vx4[4] vx4[3] vx4[2] vx4[1] vx4[0] vx4[3] vx4[2] vx4[1] vx4[0] vx4[7] vx4[6] vx4[5] vx4[4] vx4[3] vx4[2] vx4[1] vx4[0] vx4[3] vx4[2] vx4[1] vx4[0] c hsub[7] hsub[6] hsub[5] hsub[4] hsub[7] hsub[6] hsub[5] hsub[4]
data sheet orca series 2 fpgas june 1999 36 lucent technologies inc. interquad routing (continued) pic interquad (mid) routing between the pics in each quadrant, there is also con- nectivity between the pic routing and the interquad routing. these blocks are called lmid (left), tmid (top), rmid (right), and bmid (bottom). the tmid rout- ing is shown in figure 33. as with the hiq and viq blocks, the only connectivity to the pic routing is to the global pxh and pxl lines. the pxh lines from the one quadrant can be con- nected through a cip to its counterpart in the opposite quadrant, providing a path that spans the array of pics. since a passive cip is used to connect the two pxh lines, a 3-state signal can be routed on the two pxh lines in the opposite quadrants, and then connected through this cip. as with the hiq and viq blocks, cips and buffers allow nibble-wide connections between the interquad lines, the xh lines, and the xl lines. 5-4201(f).r4 figure 33. top (tmid) routing pxl[1] pxl[0] px4[3] px4[2] px4[1] px4[0] px1[3] px1[2] px1[1] px1[0] viq0[0] pxh[2] pxh[1] pxh[0] hx4[3] hx4[2] hx4[1] hx4[0] viq1[0] viq2[0] viq3[0] pxh[3] pxl[1] pxl[0] px4[3] px4[2] px4[1] px4[0] px1[3] px1[2] px1[1] px1[0] pxh[2] pxh[1] pxh[0] hx4[3] hx4[2] hx4[1] hx4[0] pxh[3]
lucent technologies inc. 37 data sheet june 1999 orca series 2 fpgas programmable corner cells programmable routing the programmable corner cell (pcc) contains the cir- cuitry to connect the routing of the two pics in each corner of the device. the pic px1 and px2 lines are directly connected together from one pic to another. the pic pxl lines are connected from one block to another through tridirectional buffers. four cips in each corner connect the four pxh lines from each side of the device. special-purpose functions in addition to routing functions, special-purpose func- tions are located in each fpga corner. the upper-left pcc contains connections to the boundary-scan logic. the upper-right pcc contains connections to the read- back logic and the connectivity to the global 3-state signal (ts_all). the lower-left pcc contains connec- tions to the internal oscillator. the lower-right pcc contains connections to the start- up and global reset logic. during configuration, the reset input pad always initiates a configuration abort, as described in the fpga states of operation section. after configuration, the global set/reset signal (gsrn) can either be disabled (the default), directly connected to the reset input pad, or sourced by a lower-right corner signal. if the reset input pad is not used as a global reset after configuration, this pad can be used as a normal input pad. during start-up, the release of the global set/reset, the release of the i/os, and the release of the external done signal can each be timed individually based upon the start-up clock. the start-up clock can come from cclk or it can be routed into the start-up block using the lower-right corner routing resources. more details on start-up can be found in the fpga states of operation section. clock distribution network the orca series 2 clock distribution schemes use pri- mary and secondary clocks. this provides the system designer with additional flexibility in assigning clock input pins. one advantage is that board-level clock traces routed to the fpga are shorter. on a pc board, the added length of high-speed clock traces routed to dedicated clock input pins can significantly increase the parasitic impedances. the primary advantage of the orca clock distribution is the availability of a large number of clocks, since all i/o pins are configurable as clocks. primary clock the primary clock distribution is shown in figure 34. if the clock signal is from an i/o pad, it can be driven onto a clock line. the clock lines do not provide clock signals directly to the pfu; they act as clock spines from which clocks are branched to xl lines. the xl lines then feed the clocks to pfus. a multiplexer in each plc is used to transition from the clock spine to the branch. for a clock spine in the horizontal direction, the inputs into the multiplexer are the two lines from the left and right pics (ckl and ckr) and the local clock line from the perpendicular direction (hck). this signal is then buffered and driven onto one of the vertical xl lines, forming the branches. the same structure is used for a clock spine in the vertical direction. in this case, the multiplexer selects from lines from the top and bottom pics (ckt, ckb, and vck) and drives the signal onto one of the horizontal xl lines. figure 34 illustrates the distribution of the low-skew pri- mary clock to a large number of loads using a main spine and branches. each row (column) has two dedi- cated clock lines originating from pics on opposite sides of the array. the clock is input from the pads to the dedicated clock line ckt to form the clock spine (see figure 34, detail a). from the clock spine, net branches are routed using horizontal xl lines and then plc clock inputs are tapped from the xl lines, as shown in figure 34, detail b.
38 lucent technologies inc. data sheet orca series 2 fpgas june 1999 clock distribution network (continued) 5-4480(f).r3 figure 34. primary clock distribution secondary clock there are times when a primary clock is either not available or not desired, and a secondary clock is needed. for example: n only one input pad per pic can be placed on the clock routing. if a second input pad in a given pic requires global signal routing, a secondary clock route must be used. n since there is only one branch driver in each plc for either direction (vertical and horizontal), both clock lines in a particular row or column (ckl and ckr, for example) cannot drive a branch. therefore, two clocks should not be placed into i/o pads in pics on the opposite sides of the same row or column if glo- bal clocks are to be used. n since the clock lines can only be driven from input pads, internally generated clocks should use second- ary clock routing. figure 35 illustrates the secondary clock distribution. if the clock signal originates from either the left or right side of the fpga, it can be routed through the tridi buffers in the pic onto one of the adjacent plcs hori- zontal xl lines. if the clock signal originates from the top or bottom of the fpga, the vertical xl lines are used for routing. in either case, an xl line is used as the clock spine. in the same manner, if a clock is only going to be used in one quadrant, the xh lines can be used as a clock spine. the routing of the clock spine from the input pads to the vxl (vxh) using the bidis (bidihs) is shown in figure 35, detail a. in each plc, a low-skew connection through a long- line driver can be used to connect a horizontal xl line to a vertical xl line or vice versa. as shown in figure 35, detail b, this is used to route the branches from the clock spine. if the clock spine is a vertical xl line, then the branches are horizontal xl lines and vice versa. the clock is then routed into each plc from the xl line clock branches. to minimize skew, the plc clock input for all plcs must be connected to the branch xl lines, not the spine xl line. even in plcs where the clock is routed from the spine to the branches, the clock should be routed back into the plc from the clock branch. if the clock is to drive only a limited number of loads, the pfus can be connected directly to the clock spine. in this case, all flip-flops driven by the clock must be located in the same row or column. ckt ckb hxl hck r7c8 hck detail b r7c7 hxl clock branch clock spines plc r1c8 plc r18c8 pic pt8 clock spine ckt detail a abcd clock clock spine see detail a see detail b clk pin branches dt dt dt dt
lucent technologies inc. 39 data sheet june 1999 orca series 2 fpgas clock distribution network (continued) alternatively, the clock can be routed from the spine to the branches by using the bidis instead of the long-line drivers. this results in added delay in the clock net, but the clock skew is approximately equal to the clock routed using the long-line drivers. this method can be used to create a clock that is used in only one quad- rant. the xh lines act as a clock spine, which is then routed to perpendicular xh lines (the branches) using the bidihs. clock signals, such as the output of a counter, can also be generated in plcs and routed onto an xl line, which then acts as a clock spine. although the clock can be generated in any plc, it is recommended that the clock be located as close to the center of the fpga as possible to minimize clock skew. selecting clock input pins any user i/o pin on an orca fpga can be used as a very fast, low-skew clock input. choosing the first clock pin is completely arbitrary, but using a pin that is near the center of an edge of the device (as shown in fig- ures 34 and 35) will provide the lowest skew clock net- work. the pin-to-pin timing numbers in the timing characteristics section of this data book assume that the clock pin is in one of the four pics at the center of any side of the device. once the first clock pin has been chosen, there are only two sets of pins (within the center four pics on each side of the device) that should not be chosen as the second clock pin: a pin from the same pic, and/or a pin from the pic on the exact opposite edge of the die (i.e., if a pin from a pic on the top edge is chosen for the first clock, the same pic on the bottom edge should not be chosen for the second clock). these rules should be followed iteratively until a total of eight clocks (or other global signals) have been selected: four from the left/right sides of the device, and four from the top/bottom sides of the device. if more than eight clocks are needed, then select another pin outside the center four pics to use primary-clock rout- ing, use secondary clock routing for any pin, or use local clock routing. if it is desired to use a pin for one of the first eight clocks that is not within the center four pics of any side of the device and primary clock routing is desired, the pad names (see pin information) of the two clock pins on the top or bottom of the device cannot be a multi- plier of four pics away. the same rule applies to clock pins on the left or right side of the device. the following equation can be used to determine pin names: pad number = p[rl][tb]n (i x 4)[a C d] where i = 18, and n is the current pic number. for more information, please refer to utilizing the orca ? or2c/txxa clock distribution network appli- cation note (ap97-055fpga). 5-4481(f).r2 figure 35. secondary clock distribution dt dt dt dt clock clock spine see detail a see detail b clk pin branches pfu hck vck detail b pa pb vxl[3] vxl[2] vxl[1] vxl[0] vxh[3] vxh[2] vxh[1] vxh[0] detail a pc pd
40 lucent technologies inc. data sheet orca series 2 fpgas june 1999 fpga states of operation prior to becoming operational, the fpga goes through a sequence of states, including initialization, configuration, and start-up. figure 36 outlines these three fpga states. 5-4529(f).r6 figure 36. fpga states of operation initialization upon powerup, the device goes through an initialization process. first, an internal power-on-reset circuit is trig- gered when power is applied. when v dd reaches the voltage at which portions of the fpga begin to operate (2.5 v to 3 v for the or2cxxa, 2.2 v to 2.7 v for the or2txxa/or2txxb), the i/os are configured based on the configuration mode, as determined by the mode select inputs m[2:0]. a time-out delay is initiated when v dd reaches between 3.0 v and 4.0 v (or2cxxa) or 2.7 v to 3.0 v (or2txxa/2txxb) to allow the power supply voltage to stabilize. the init and done outputs are low. at powerup, if v dd does not rise from 2.0 v to v dd in less than 25 ms, the user should delay configu- ration by inputting a low into init , prgm , or reset until v dd is greater than the recommended minimum operating voltage (4.75 v for or2cxxa commercial devices and 3.0 v for or2txxa/b devices). at the end of initialization, the default configuration option is that the configuration ram is written to a low state. this prevents shorts prior to configuration. as a configuration option, after the first configuration (i.e., at reconfiguration), the user can reconfigure without clearing the internal configuration ram first. the active-low, open-drain initialization signal init is released and must be pulled high by an external resis- tor when initialization is complete. to synchronize the configuration of multiple fpgas, one or more init pins should be wire-anded. if init is held low by one or more fpgas or an external device, the fpga remains in the initialization state. init can be used to signal that the fpgas are not yet initialized. after init goes high for two internal clock cycles, the mode lines (m[3:0]) are sampled and the fpga enters the configuration state. the high during configuration (hdc), low during config- uration (ldc ), and done signals are active outputs in the fpgas initialization and configuration states. hdc, ldc , and done can be used to provide control of external logic signals such as reset, bus enable, or prom enable during configuration. for parallel master configuration modes, these signals provide prom enable control and allow the data pins to be shared with user logic signals. if configuration has begun, an assertion of reset or prgm initiates an abort, returning the fpga to the ini- tialization state. the prgm and reset pins must be pulled back high before the fpga will enter the config- uration state. during the start-up and operating states, only the assertion of prgm causes a reconfiguration. in the master configuration modes, the fpga is the source of configuration clock (cclk). in this mode, the initialization state is extended to ensure that, in daisy- chain operation, all daisy-chained slave devices are ready. independent of differences in clock rates, master mode devices remain in the initialization state an addi- tional six internal clock cycles after init goes high. when configuration is initiated, a counter in the fpga is set to 0 and begins to count configuration clock cycles applied to the fpga. as each configuration data frame is supplied to the fpga, it is internally assem- bled into data words. each data word is loaded into the internal configuration memory. the configuration load- ing process is complete when the internal length count equals the loaded length count in the length count field, and the required end of configuration frame is written. C active i/o C release internal reset C done goes high start-up initialization configuration reset or prgm low prgm low C clear configuration memory C init low, hdc high, ldc low operation powerup C power-on time delay C m[3:0] mode is selected C configuration data frame written C init high, hdc high, ldc low C dout active yes no no reset , init , or prgm low bit error yes
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 41 fpga states of operation (continued) 5-4482(f) figure 37. initialization/configuration/start-up waveforms initialization configuration start-up operation v dd reset prgm init m[3:0] cclk hdc ldc done user i/o internal reset (gsm) all or2cxxa i/os operate as ttl inputs during config- uration (or2txxa/or2txxb i/os are cmos-only). all i/os that are not used during the configuration process are 3-stated with internal pull-ups. during configura- tion, the plc latch/ffs are held set/reset and the inter- nal bidi buffers are 3-stated. the tridis in the pics are not 3-stated. the combinatorial logic begins to function as the fpga is configured. figure 37 shows the general waveform of the initialization, configuration, and start-up states. configuration the orca series fpga functionality is determined by the state of internal configuration ram. this configura- tion ram can be loaded in a number of different modes. in these configuration modes, the fpga can act as a master or a slave of other devices in the sys- tem. the decision as to which configuration mode to use is a system design issue. the next section dis- cusses configuration in detail, including the configura- tion data format and the configuration modes used to load the configuration data in the fpga.
42 lucent technologies inc. data sheet orca series 2 fpgas june 1999 fpga states of operation (continued) start-up after configuration, the fpga enters the start-up phase. this phase is the transition between the config- uration and operational states and begins when the number of cclks received after init goes high is equal to the value of the length count field in the configuration frame and when the end of configuration frame has been written. the system design issue in the start-up phase is to ensure the user i/os become active without inadvertently activating devices in the system or caus- ing bus contention. a second system design concern is the timing of the release of global set/reset of the plc latches/ffs. there are configuration options that control the relative timing of three events: done going high, release of the set/reset of internal ffs, and user i/os becoming active. figure 38 shows the start-up timing for both the orca and att3000 series fpgas. the system designer determines the relative timing of the i/os becoming active, done going high, and the release of the set/reset of internal ffs. in the orca series fpga, the three events can occur in any arbitrary sequence. this means that they can occur before or after each other, or they can occur simultaneously. there are four main start-up modes: cclk_nosync, cclk_sync, uclk_nosync, and uclk_sync. the only difference between the modes starting with cclk and those starting with uclk is that for the uclk modes, a user clock must be supplied to the start-up logic. the timing of start-up events is then based upon this user clock, rather than cclk. the dif- ference between the sync and nosync modes is that, for sync mode, the timing of two of the start-up events (release of the set/reset of internal ffs and the i/os becoming active) is triggered by the rise of the external done pin followed by a variable number of ris- ing clock edges (either cclk or uclk). for the nosync mode, the timing of these two events is based only on either cclk or uclk. done is an open-drain bidirectional pin that may include an optional (enabled by default) pull-up resistor to accommodate wired anding. the open-drain done signals from multiple fpgas can be tied together (anded) with a pull-up (internal or external) and used as an active-high ready signal, an active-low prom enable, or a reset to other portions of the system. when used in sync mode, these anded done pins can be used to synchronize the other two start-up events, since they can all be synchronized to the same external signal. this signal will not rise until all fpgas release their done pins, allowing the signal to be pulled high. the default for orca is the cclk_sync synchro- nized start-up mode where done is released on the first cclk rising edge, c1 (see figure 38). since this is a synchronized start-up mode, the open-drain done signal can be held low externally to stop the occurrence of the other two start-up events. once the done pin has been released and pulled up to a high level, the other two start-up events can be programmed individu- ally to either happen immediately or after up to four ris- ing edges of cclk (di, di + 1, di + 2, di + 3, di + 4). the default is for both events to happen immediately after done is released and pulled high. a commonly used design technique is to release done one or more clock cycles before allowing the i/o to become active. this allows other configuration devices, such as proms, to be disconnected using the done signal so that there is no bus contention when the i/os become active. in addition to controlling the fpga during start-up, other start-up techniques that avoid contention include using isolation devices between the fpga and other circuits in the system, reassigning i/o locations and maintaining i/os as 3-stated outputs until contentions are resolved. each of these start-up options can be selected during bit stream generation in orca foundry, using advanced options. for more information, please see the orca foundry documentation. reconfiguration to reconfigure the fpga when the device is operating in the system, a low pulse is input into prgm . the con- figuration data in the fpga is cleared, and the i/os not used for configuration are 3-stated. the fpga then samples the mode select inputs and begins reconfigu- ration. when reconfiguration is complete, done is released, allowing it to be pulled high.
lucent technologies inc. 43 data sheet june 1999 orca series 2 fpgas fpga states of operation (continued) 5-2761(f).r4 figure 38. start-up waveforms partial reconfiguration all orca device families have been designed to allow a partial reconfiguration of the fpga at any time. this is done by setting a bit stream option in the previous configuration sequence that tells the fpga to not reset all of the configuration ram during a reconfiguration. then only the configuration frames that are to be modi- fied need to be rewritten, thereby reducing the configu- ration time. other bit stream options are also available that allow one portion of the fpga to remain in operation while a partial reconfiguration is being done. if this is done, the user must be careful to not cause contention between the two configurations (the bit stream resident in the fpga and the partial reconfiguration bit stream) as the second reconfiguration bit stream is being loaded. other configuration options configuration options used during device start-up were previously discussed in the fpga states of operation section of this data sheet. there are many other config- uration options available to the user that can be set during bit stream generation in orca foundry. these include options to enable boundary scan, readback options, and options to control and use the internal oscillator after configuration. other useful options that affect the next configuration (not the current configuration process) include options to disable the global set/reset during configuration, dis- able the 3-state of i/os during configuration, and dis- able the reset of internal rams during configuration to allow for partial configurations (see above). for more information on how to set these and other configuration options, please see the orca foundry documenta- tion. configuration data format the orca foundry development system interfaces with front-end design entry tools and provides the tools to produce a fully configured fpga. this section dis- cusses using the orca foundry development system to generate configuration ram data and then provides the details of the configuration frame format. the orca series 2 series of fpgas are enhanced versions of the orca att2cxx/att2txx architectures that provide upward bit stream compatibility for both series of devices as well as with each other. di f done att3000 i/o global reset c1 c2 c3 c4 f c1 c2 c3 c4 c1 c2 c3 c4 c1, c2, c3, or c4 di + 1 di di + 2 di + 3 di + 4 di + 1 di di + 2 di + 3 di + 4 orca cclk_sync done in u1 u2 u3 u4 f u1 u2 u3 u4 u1 u2 u3 u4 orca uclk_nosync di + 1 di di + 2 di + 3 di + 4 di + 1 di + 2 di + 3 orca uclk_sync uclk period synchronization uncertainty done in f c1 c1 u1, u2, u3, or u4 done i/o gsrn active done i/o gsrn active done i/o gsrn active done i/o gsrn active uclk f = finished, no more clks required. cclk period f orca cclk_nosync
data sheet orca series 2 fpgas june 1999 44 lucent technologies inc. configuration data format (continued) using orca foundry to generate configuration ram data the configuration data defines the i/o functionality, logic, and interconnections. the bit stream is gener- ated by the development system. the bit stream cre- ated by the bit stream generation tool is a series of 1s and 0s used to write the fpga configuration ram. the bit stream can be loaded into the fpga using one of the configuration modes discussed later. in the bit stream generator, the designer selects options which affect the fpgas functionality. using the output of the bit stream generator, circuit.bit, the development sys- tems download tool can load the configuration data into the orca series fpga evaluation board from a pc or workstation. alternatively, a user can program a prom (such as the att1700a series serial rom or a standard eprom) and load the fpga from the prom. the development systems prom programming tool produces a file in .mks or .exo format. configuration data frame a detailed description of the frame format is shown in figure 39. the header frame begins with a series of 1s and a preamble of 0010, followed by a 24-bit length count field representing the total number of configura- tion clocks needed to complete the loading of the fpgas. following the header frame is an optional id frame. this frame contains data used to determine if the bit stream is being loaded to the correct type of orca fpga (i.e., a bit stream generated for an or2c15a is being sent to an or2c15a). since the or2cxxa devices are bit stream compatible with the att2cxx, att2txx, or2txxa, and or2txxb families, a bit stream from any of these devices will not cause an error when loaded into an or2cxxa, or2txxa, or or2txxb device. the id frame has a secondary func- tion of optionally enabling the parity checking logic for the rest of the data frames. the configuration data frames follow. each frame starts with a 0 start bit and ends with three or more 1 stop bits. following each start bit are four control bits: a pro- gram bit, set to 1 if this is a data frame; a compress bit, set to 1 if this is a compressed frame; and the opar and epar parity bits (see bit stream error checking). an 11-bit address field that determines in which column the fpga is to be written is followed by alignment and write control bits. for uncompressed frames, the data bits needed to write one column in the fpga are next. for compressed frames, the data bits from the previous frame are sent to a different fpga column, as speci- fied by the new address bits; therefore, new data bits are not required. when configuration of the current fpga is finished, an end-of-configuration frame (where the program bit is set to 0) is sent to the fpga. the length and number of data frames and information on the prom size for the series 3 fpgas are given in table 7. table 7. configuration frame size devices or2c/ 2t04a or2c/ 2t06a or2c/ 2t08a or2c/ 2t10a or2c/ 2t12a or2c/ 2t15a/b or2c/ 2t26a or2c/ 2t40a/b # of frames 480 568 656 744 832 920 1096 1378 data bits/frame 110 130 150 170 190 210 250 316 configuration data (# of frames x # of data bits/frame) 52,800 73,840 98,400 126,480 158,080 193,200 274,000 435,448 maximum total # bits/frame (align bits, 1 write bit, 8 stop bits) 136 160 176 200 216 240 280 344 maximum configuration data (# bits x # of frames) 65,280 90,880 115,456 148,800 179,712 220,800 306,880 474,032 maximum prom size (bits) (add 48-bit header, id frame, and 40-bit end of configuration frame) 65,504 91,128 115,720 149,088 180,016 221,128 307,248 474,464
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 45 configuration data format (continued) the data frames for all the series 2 series devices are given in table 8. an alignment field is required in the slave parallel mode for the uncompressed format. the alignment field (shown by [a]) is a series of 0s: five for the or2c06a/or2t06a, or2c10a/or2t10a, or2c15a/or2t15a/or2t15b, and or2c26a/or2t26a; three for the or2c40a/or2t40a/or2t40b; and one for the or2c04a/or2t04a, or2c08a/or2t08a, and or2c12a/ or2t12a. the alignment field is not required in any other mode. table 8. configuration data frames 5-4530(f) figure 39. serial configuration data format or2c04a/or2t04a uncompressed 010 opar epar [addr10:0] [a]1[data109:0]111 compressed 011 opar epar [addr10:0] 111 or2c06a/or2t06a uncompressed 010 opar epar [addr10:0] [a]1[data129:0]111 compressed 011 opar epar [addr10:0] 111 or2c08a/or2t08a uncompressed 010 opar epar [addr10:0] [a]1[data149:0]111 compressed 011 opar epar [addr10:0] 111 or2c10a/or2t10a uncompressed 010 opar epar [addr10:0] [a]1[data169:0]111 compressed 011 opar epar [addr10:0] 111 or2c12a/or2t12a uncompressed 010 opar epar [addr10:0] [a]1[data189:0]111 compressed 011 opar epar [addr10:0] 111 or2c15a/or2t15a/or2t15b uncompressed 010 opar epar [addr10:0] [a]1[data209:0]111 compressed 011 opar epar [addr10:0] 111 or2c26a/or2t26a uncompressed 010 opar epar [addr10:0] [a]1[data249:0]111 compressed 011 opar epar [addr10:0] 111 or2c40a/or2t40a/or2t40b uncompressed 010 opar epar [addr10:0] [a]1[data315:0]111 compressed 011 opar epar [addr10:0] 111 eight 1s 0010 24-bit length count postamble leading header data frames fpga #1 data frames fpga #2 end of configuration frame fpga #1 end of configuration frame fpga #2 preamble
data sheet orca series 2 fpgas june 1999 46 lucent technologies inc. configuration data format (continued) table 9. configuration frame format and contents note: for slave parallel mode, the byte containing the preamble must be 11110010. the number of leading header dummy bits must be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive integer. the number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. note also that the bit stream generator tool supplies a bit stream which is compatible with all configuration modes, including slave parallel mode. header 11111111 leading header4 bits minimum dummy bits 0010 preamble 24-bit length count configuration frame length 1111 trailing header4 bits minimum dummy bits id frame (optional) 0 frame start p1 must be set to 1 to indicate data frame c0 must be set to 0 to indicate uncompressed opar, epar frame parity bits addr[10:0] = 11111111111 id frame address prty_en set to 1 to enable parity reserved [42:0] reserved bits set to 0 id 20-bit part id 111 three or more stop bits (high) to separate frames configuration data frame (repeated for each data frame) 0 frame start p1 or 0 1 indicates data frame; 0 indicates all frames are written c1 or 0 uncompressed0 indicates data and address are supplied; compressed1 indicates only address is supplied opar, epar frame parity bits addr[10:0] column address in fpga to be written a alignment bit (different number of 0s needed for each part) 1 write bitused in uncompressed data frame data bits needed only in an uncompressed data frame .. .. 111 one or more stop bits (high) to separate frames end of configuration 0010011111111111 16 bits00 indicates all frames are written postamble 111111 . . . . . additional 1s
lucent technologies inc. 47 data sheet june 1999 orca series 2 fpgas bit stream error checking there are three different types of bit stream error checking performed in the orca series 2 fpgas: id frame, frame alignment, and parity checking. an optional id data frame can be sent to a specified address in the fpga. this id frame contains a unique code for the part it was generated for which is com- pared within the fpga. any differences are flagged as an id error. this frame is automatically created by the bit stream generation program in orca foundry. every data frame in the fpga begins with a start bit set to 0 and three or more stop bits set to 1. if any of the three previous bits were a 0 when a start bit is encountered, it is flagged as a frame alignment error. parity checking is also done on the fpga for each frame, if it has been enabled by setting the prty_en bit to 1 in the id frame. this is set by enabling the parity check option in the bit stream generation program of orca foundry. two parity bits, opar and epar, are used to check the parity of bits in alternating bit posi- tions to even parity in each data frame. if an odd num- ber of ones is found for either the even bits (starting with the start bit) or the odd bits (starting with the pro- gram bit), then a parity error is flagged. when any of the three possible errors occur, the fpga is forced into the init state, forcing init low. the fpga will remain in this state until either the reset or prgm pins are asserted. fpga configuration modes there are eight methods for configuring the fpga. seven of the configuration modes are selected on the m0, m1, and m2 inputs. the eighth configuration mode is accessed through the boundary-scan interface. a fourth input, m3, is used to select the frequency of the internal oscillator, which is the source for cclk in some configuration modes. the nominal frequencies of the internal oscillator are 1.25 mhz and 10 mhz. the 1.25 mhz frequency is selected when the m3 input is unconnected or driven to a high state. there are three basic fpga configuration modes: master, slave, and peripheral. the configuration data can be transmitted to the fpga serially or in parallel bytes. as a master, the fpga provides the control sig- nals out to strobe data in. as a slave device, a clock is generated externally and provided into cclk. in the peripheral mode, the fpga acts as a microprocessor peripheral. table 10 lists the functions of the configura- tion mode pins. table 10. configuration modes master parallel mode the master parallel configuration mode is generally used to interface to industry-standard byte-wide mem- ory, such as the 2764 and larger eproms. figure 40 provides the connections for master parallel mode. the fpga outputs an 18-bit address on a[17:0] to memory and reads one byte of configuration data on the rising edge of rclk. the parallel bytes are internally serial- ized starting with the least significant bit, d0. 5-4483(f) figure 40. master parallel configuration schematic there are two parallel master modes: master up and master down. in master up, the starting memory address is 00000 hex and the fpga increments the address for each byte loaded. in master down, the starting memory address is 3ffff hex and the fpga decrements the address. one master mode fpga can interface to the memory and provide configuration data on dout to additional fpgas in a daisy chain. the configuration data on dout is provided synchronously with the falling edge of cclk. the frequency of the cclk output is eight times that of rclk. m2 m1 m0 cclk configuration mode data 0 0 0 output master serial 0 0 1 input slave parallel parallel 010reserved 0 1 1 input sync peripheral parallel 1 0 0 output master (up) parallel 1 0 1 output async peripheral parallel 1 1 0 output master (down) parallel 1 1 1 input slave serial to daisy- chained devices dout cclk hdc ldc rclk a[17:0] d[7:0] done prgm m2 m1 m0 a[17:0] d[7:0] oe ce program v dd v dd or gnd eprom orca series fpga
48 lucent technologies inc. data sheet orca series 2 fpgas june 1999 fpga configuration modes (continued) master serial mode in the master serial mode, the fpga loads the configu- ration data from an external serial rom. the configura- tion data is either loaded automatically at start-up or on a prgm command to reconfigure. the att1700 and att1700a series can be used to configure the fpga in the master serial mode. this provides a simple 4-pin interface in an 8-pin package. the att1736, att1765, and att17128 serial roms store 32k, 64k, and 128k bits, respectively. configuration in the master serial mode can be done at powerup and/or upon a configure command. the sys- tem or the fpga must activate the serial rom's reset /oe and ce inputs. at powerup, the fpga and serial rom each contain internal power-on reset cir- cuitry that allows the fpga to be configured without the system providing an external signal. the power-on reset circuitry causes the serial rom's internal address pointer to be reset. after powerup, the fpga automati- cally enters its initialization phase. the serial rom/fpga interface used depends on such factors as the availability of a system reset pulse, avail- ability of an intelligent host to generate a configure command, whether a single serial rom is used or mul- tiple serial roms are cascaded, whether the serial rom contains a single or multiple configuration pro- grams, etc. because of differing system requirements and capabilities, a single fpga/serial rom interface is generally not appropriate for all applications. data is read in the fpga sequentially from the serial rom. the data output from the serial rom is con- nected directly into the din input of the fpga. the cclk output from the fpga is connected to the clock input of the serial rom. during the configura- tion process, cclk clocks one data bit on each rising edge. since the data and clock are direct connects, the fpga/serial rom design task is to use the system or fpga to enable the reset /oe and ce of the serial rom(s). there are several methods for enabling the serial roms reset /oe and ce inputs. the serial rom's reset /oe is programmable to function with reset active-high and oe active-low or reset active- low and oe active-high. in figure 41, serial roms are cascaded to configure multiple daisy-chained fpgas. the host generates a 500 ns low pulse into the fpga's prgm input. the fpgas init input is connected to the serial roms reset /oe input, which has been programmed to function with reset active-low and oe active-high. the fpga done is routed to the ce pin. the low on done enables the serial roms. at the completion of configuration, the high on the fpga's done disables the serial rom. serial roms can also be cascaded to support the con- figuration of multiple fpgas or to load a single fpga when configuration data requirements exceed the capacity of a single serial rom. after the last bit from the first serial rom is read, the serial rom outputs ceo low and 3-states the data output. the next serial rom recognizes the low on ce input and outputs con- figuration data on the data output. after configuration is complete, the fpgas done output into ce disables the serial roms. this fpga/serial rom interface is not used in applica- tions in which a serial rom stores multiple configura- tion programs. in these applications, the next configuration program to be loaded is stored at the rom location that follows the last address for the previ- ous configuration program. the reason the interface in figure 41 will not work in this application is that the low output on the init signal would reset the serial rom address pointer, causing the first configuration to be reloaded. in some applications, there can be contention on the fpga's din pin. during configuration, din receives configuration data, and after configuration, it is a user i/o. if there is contention, an early done at start-up (selected in orca foundry) may correct the problem. an alternative is to use ldc to drive the serial rom's ce pin. in order to reduce noise, it is generally better to run the master serial configuration at 1.25 mhz (m3 pin tied high), rather than 10 mhz, if possible. figure 41. master serial configuration schematic att1700a din m2 m1 m0 orca series fpga cclk dout to daisy- chained devices data clk ce ceo att1700a data clk reset /oe ceo ce to more serial roms as needed done init program reset /oe prgm 5-4456.1(f)
lucent technologies inc. 49 data sheet june 1999 orca series 2 fpgas fpga configuration modes (continued) asynchronous peripheral mode figure 42 shows the connections needed for the asyn- chronous peripheral mode. in this mode, the fpga system interface is similar to that of a microprocessor- peripheral interface. the microprocessor generates the control signals to write an 8-bit byte into the fpga. the fpga control inputs include active-low cs0 and active- high cs1 chip selects, a write wr input, and a read rd input. the chip selects can be cycled or maintained at a static level during the configuration cycle. each byte of data is written into the fpgas d[7:0] input pins. the fpga provides a rdy status output to indicate that another byte can be loaded. a low on rdy indi- cates that the double-buffered hold/shift registers are not ready to receive data, and this pin must be moni- tored to go high before another byte of data can be written. the shortest time rdy is low occurs when a byte is loaded into the hold register and the shift regis- ter is empty, in which case the byte is immediately transferred to the shift register. the longest time for rdy to remain low occurs when a byte is loaded into the holding register and the shift register has just started shifting configuration data into configuration ram. the rdy status is also available on the d7 pin by enabling the chip selects, setting wr high, and apply- ing rd low, where the rd input is an output enable for the d7 pin when rd is low. the d[6:0] pins are not enabled to drive when rd is low and, thus, only act as input pins in asynchronous peripheral mode. 5-4484(f) figure 42. asynchronous peripheral configuration schematic synchronous peripheral mode in the synchronous peripheral mode, byte-wide data is input into d[7:0] on the rising edge of the cclk input. the first data byte is clocked in on the second cclk after init goes high. subsequent data bytes are clocked in on every eighth rising edge of cclk. the rdy signal is an output which acts as an acknowledge. rdy goes high one cclk after data is clocked and, after one cclk cycle, returns low. the process repeats until all of the data is loaded into the fpga. the data begins shifting on dout 1.5 cycles after it is loaded in parallel. it requires additional cclks after the last byte is loaded to complete the shifting. figure 43 shows the connections for synchronous peripheral mode. as with master modes, the peripheral modes can be used as the lead fpga for a daisy chain of slave fpgas. 5-4486(f) figure 43. synchronous peripheral configuration schematic to daisy- chained devices dout cclk hdc ldc v dd orca series fpga micro- processor address decode logic bus controller prgm d[7:0] rdy/busy init done cs0 cs1 rd wr m2 m1 m0 8 to daisy- chained devices dout hdc ldc orca series fpga micro- processor prgm d[7:0] m2 m1 m0 8 +5 v cclk rdy/busy init
50 lucent technologies inc. data sheet orca series 2 fpgas june 1999 fpga configuration modes (continued) slave serial mode the slave serial mode is primarily used when multiple fpgas are configured in a daisy chain. the serial slave serial mode is also used on the fpga evaluation board which interfaces to the download cable. a device in the slave serial mode can be used as the lead device in a daisy chain. figure 44 shows the connections for the slave serial configuration mode. the configuration data is provided into the fpgas din input synchronous with the configuration clock cclk input. after the fpga has loaded its configuration data, it retransmits the incoming configuration data on dout. cclk is routed into all slave serial mode devices in parallel. multiple slave fpgas can be loaded with identical con- figurations simultaneously. this is done by loading the configuration data into the din inputs in parallel. 5-4485(f) figure 44. slave serial configuration schematic slave parallel mode the slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins d[7:0] for each cclk cycle. due to 8 bits of data being input per cclk cycle, the dout pin does not contain a valid bit stream for slave parallel mode. as a result, the lead device cannot be used in the slave parallel mode in a daisy-chain configuration. figure 45 is a schematic of the connections for the slave parallel configuration mode. wr and cs0 are active-low chip select signals, and cs1 is an active- high chip select signal. these chip selects allow the user to configure multiple fpgas in slave parallel mode using an 8-bit data bus common to all of the fpgas. these chip selects can then be used to select the fpga(s) to be configured with a given bit stream, but once an fpga has been selected, it cannot be deselected until it has been completely programmed. 5-4487(f) figure 45. slave parallel configuration schematic micro- processor or download cable m2 m1 m0 hdc series fpga ldc v dd cclk prgm dout to daisy- chained devices done din init orca micro- processor or system d[7:0] done cclk cs1 m2 m1 m0 hdc ldc 8 v dd init prgm cs0 wr series fpga orca
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 51 fpga configuration modes (continued) daisy chain multiple fpgas can be configured by using a daisy chain of the fpgas. daisy chaining uses a lead fpga and one or more fpgas configured in slave serial mode. the lead fpga can be configured in any mode except slave parallel mode. (daisy chaining is not avail- able with the boundary-scan ram_w instruction, dis- cussed later.) all daisy-chained fpgas are connected in series. each fpga reads and shifts the preamble and length count in on positive cclk and out on negative cclk edges. an upstream fpga that has received the preamble and length count outputs a high on dout until it has received the appropriate number of data frames so that downstream fpgas do not receive frame start bits (0s). after loading and retransmitting the preamble and length count to a daisy chain of slave devices, the lead device loads its configuration data frames. the loading of configuration data continues after the lead device has received its configuration data if its internal frame bit counter has not reached the length count. when the configuration ram is full and the number of bits received is less than the length count field, the fpga shifts any additional data out on dout. the configuration data is read into din of slave devices on the positive edge of cclk, and shifted out dout on the negative edge of cclk. figure 46 shows the connections for loading multiple fpgas in a daisy- chain configuration. the generation of cclk for the daisy-chained devices which are in slave serial mode differs depending on the configuration mode of the lead device. a master paral- lel mode device uses its internal timing generator to produce an internal cclk at eight times its memory address rate (rclk). the asynchronous peripheral mode device outputs eight cclks for each write cycle. if the lead device is configured in either synchronous peripheral or a slave mode, cclk is routed to the lead device and to all of the daisy-chained devices. the development system can create a composite configuration bit stream for configuring daisy-chained fpgas. the frame format is a preamble, a length count for the total bit stream, multiple concatenated data frames, an end-of-configuration frame per device, a postamble, and an additional fill bit per device in the serial chain. as seen in figure 46, the init pins for all of the fpgas are connected together. this is required to guarantee that powerup and initialization will work correctly. in general, the done pins for all of the fpgas are also connected together as shown to guarantee that all of the fpgas enter the start-up state simultaneously. this may not be required, depending upon the start-up sequence desired. 5-4488(f) figure 46. daisy-chain configuration schematic v dd eprom program d[7:0] oe ce a[17:0] a[17:0] d[7:0] done m2 m1 m0 done hdc ldc rclk cclk dout din dout din cclk done dout init init init cclk v dd v dd or gnd prgm prgm m2 m1 m0 prgm m2 m1 m0 v dd v dd hdc ldc rclk hdc ldc rclk v dd orca series fpga slave #2 orca series fpga master orca series fpga slave #1
52 lucent technologies inc. data sheet orca series 2 fpgas june 1999 special function blocks special function blocks in the series 2 provide extra capabilities beyond general fpga operation. these blocks reside in the corners of the fpga array. single function blocks most of the special function blocks perform a specific dedicated function. these functions are data/configura- tion readback control, global 3-state control (ts_all), internal oscillator generation, global set/reset (gsrn), and start-up logic. readback logic the readback logic is located in the upper right corner of the fpga. readback is used to read back the configuration data and, optionally, the state of the pfu outputs. a read- back operation can be done while the fpga is in nor- mal system operation. the readback operation cannot be daisy-chained. to use readback, the user selects options in the bit stream generator in the orca foundry development system. table 11 provides readback options selected in the bit stream generator tool. the table provides the number of times that the configuration data can be read back. this is intended primarily to give the user control over the security of the fpgas configuration program. the user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (u). table 11. readback options the pins used for readback are readback data (rd_data), read configuration ( rd_cfg ), and configu- ration clock (cclk). a readback operation is initiated by a high-to-low transition on rd_cfg . the rd_cfg input must remain low during the readback operation. the readback operation can be restarted at frame 0 by driving the rd_cfg pin high, applying at least two ris- ing edges of cclk, and then driving rd_cfg low again. one bit of data is shifted out on rd_data at the rising edge of cclk. the first start bit of the readback frame is transmitted out several cycles after the first ris- ing edge of cclk after rd_cfg is input low (see table 48, readback timing characteristics in the timing characteristics section). it should be noted that the rd_data output pin is also used as the dedicated boundary-scan output pin, tdo. if this pin is being used as tdo, the rd_data output from readback can be routed internally to any other pin desired. the rd_cfg input pin is also used to control the global 3-state (ts_all) function. before and during configuration, the ts_all signal is always driven by the rd_cfg input and readback is disabled. after con- figuration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. if used as the rd_cfg input for readback, the internal ts_all input can be routed internally to be driven by any input pin. the readback frame contains the configuration data and the state of the internal logic. during readback, the value of all five pfu outputs can be captured. the fol- lowing options are allowed when doing a capture of the pfu outputs. 1. do not capture data (the data written to the capture rams, usually 0, will be read back). 2. capture data upon entering readback. 3. capture data based upon a configurable signal internal to the fpga. if this signal is tied to logic 0, capture rams are written continuously. 4. capture data on either options 2 or 3 above. the readback frame has a similar, but not identical, for- mat to the configuration frame. this eases a bitwise comparison between the configuration and readback data. the readback data is not inverted. every data frame has one low start bit and one high stop bit. the preamble, including the length count field, is not part of the readback frame. the readback frame contains states in locations not used in the configuration. these locations need to be masked out when comparing the configuration and readback frames. the development system optionally provides a readback bit stream to compare to readback from the fpga. also note that if any of the luts are used as ram and new data is writ- ten to them, these bits will not have the same values as the original configuration data frame either. option function 0 prohibit readback 1 allow one readback only u allow unrestricted number of readbacks
lucent technologies inc. 53 data sheet june 1999 orca series 2 fpgas special function blocks (continued) global 3-state control (ts_all) the ts_all block resides in the upper-right corner of the fpga array. to increase the testability of the orca series fpgas, the global 3-state function (ts_all) disables the device. the ts_all signal is driven from either an external pin or an internal signal. before and during configuration, the ts_all signal is driven by the input pad rd_cfg . after configuration, the ts_all signal can be disabled, driven from the rd_cfg input pad, or driven by a general routing signal in the upper-right cor- ner. before configuration, ts_all is active-low; after configuration, the sense of ts_all can be inverted. the following occur when ts_all is activated: 1. all of the user i/o output buffers are 3-stated, the user i/o input buffers are pulled up (with the pull- down disabled), and the input buffers are configured with ttl input thresholds (or2cxxa only). 2. the tdo/rd_data output buffer is 3-stated. 3. the rd_cfg , reset , and prgm input buffers remain active with a pull-up. 4. the done output buffer is 3-stated, and the input buffer is pulled-up. internal oscillator the internal oscillator resides in the lower-left corner of the fpga array. it has output clock frequencies of 1.25 mhz and 10 mhz. the internal oscillator is the source of the internal cclk used for configuration. it may also be used after configuration as a general- purpose clock signal. global set/reset (gsrn) the gsrn logic resides in the lower-right corner of the fpga. gsrn is an invertible, default, active-low signal that is used to reset all of the user-accessible latches/ ffs on the device. gsrn is automatically asserted at powerup and during configuration of the device. the timing of the release of gsrn at the end of config- uration can be programmed in the start-up logic described below. following configuration, gsrn may be connected to the reset pin via dedicated routing, or it may be connected to any signal via normal routing. within each pfu, individual ffs and latches can be programmed to either be set or reset when gsrn is asserted. the reset input pad has a special relationship to gsrn. during configuration, the reset input pad always initiates a configuration abort, as described in the fpga states of operation section. after configura- tion, the global set/reset signal (gsrn) can either be disabled (the default), directly connected to the reset input pad, or sourced by a lower-right corner signal. if the reset input pad is not used as a global reset after configuration, this pad can be used as a normal input pad. start-up logic the start-up logic block is located in the lower right cor- ner of the fpga. this block can be configured to coor- dinate the relative timing of the release of gsrn, the activation of all user i/os, and the assertion of the done signal at the end of configuration. if a start-up clock is used to time these events, the start-up clock can come from cclk, or it can be routed into the start- up block using lower-right corner routing resources. these signals are described in the start-up subsection of the fpga states of operation section.
54 lucent technologies inc. data sheet orca series 2 fpgas june 1999 special function blocks (continued) boundary scan the increasing complexity of integrated circuits (ics) and ic packages has increased the difficulty of testing printed-circuit boards (pcbs). to address this testing problem, the ieee standard 1149.1 - 1990 ( ieee stan- dard test access port and boundary-scan architec- ture) is implemented in the orca series of fpgas. it allows users to efficiently test the interconnection between integrated circuits on a pcb as well as test the integrated circuit itself. the ieee 1149.1 standard is a well-defined protocol that ensures interoperability among boundary-scan (bscan) equipped devices from different vendors. the ieee 1149.1 standard defines a test access port (tap) that consists of a 4-pin interface with an optional reset pin for boundary-scan testing of integrated cir- cuits in a system. the orca series fpga provides four interface pins: test data in (tdi), test mode select (tms), test clock (tck), and test data out (tdo). the prgm pin used to reconfigure the device also resets the boundary-scan logic. the user test host serially loads test commands and test data into the fpga through these pins to drive out- puts and examine inputs. in the configuration shown in figure 47, where boundary scan is used to test ics, test data is transmitted serially into tdi of the first bscan device (u1), through tdo/tdi connections between bscan devices (u2 and u3), and out tdo of the last bscan device (u4). in this configuration, the tms and tck signals are routed to all boundary-scan ics in parallel so that all boundary-scan components operate in the same state. in other configurations, mul- tiple scan paths are used instead of a single ring. when multiple scan paths are used, each ring is indepen- dently controlled by its own tms and tck signals. figure 48 provides a system interface for components used in the boundary-scan testing of pcbs. the three major components shown are the test host, boundary- scan support circuit, and the devices under test (duts). the duts shown here are orca series fpgas with dedicated boundary-scan circuitry. the test host is normally one of the following: automatic test equipment (ate), a workstation, a pc, or a micropro- cessor. fig.34.a(f).1c key: bsc = boundary-scan cell, bdc = bidirectional data cell, and dcc = data control cell. figure 47. printed-circuit board with boundary- scan circuitry the boundary-scan support circuit shown in figure 48 is the 497aa boundary-scan master (bsm). the bsm off-loads tasks from the test host to increase test throughput. to interface between the test host and the duts, the bsm has a general microprocessor interface and provides parallel-to-serial/serial-to-parallel conver- sion, as well as three 8k data buffers. scan out tdi tms tck tdo u2 see enlarged view below plc array scan in tdo tck tms tdi tapc bypass register instruction register bdc bsc p_in p_out p_ts scan in pt[ij] enlarged view tdi tdo tms tck u1 tdi tdo tms tck u4 tdi tdo tms tck u3 tdi tdo tms tck net a net b net c s dcc scan out dcc bsc p_in p_out p_ts scan in pb[ij] bdc scan out bdc bsc p_in p_out p_ts pr[ij] dcc scan out bsc p_in p_out p_ts pl[ij] scan in dcc bdc
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 55 special function blocks (continued) 5-4488(f) figure 48. boundary-scan interface v dd eprom program d[7:0] oe ce a[17:0] a[17:0] d[7:0] done m2 m1 m0 done hdc ldc rclk cclk dout din dout din cclk done dout init init init cclk v dd v dd or gnd prgm prgm m2 m1 m0 prgm m2 m1 m0 v dd v dd hdc ldc rclk hdc ldc rclk v dd orca series fpga slave #2 orca series fpga master orca series fpga slave #1 the bsm also increases test throughput with a dedi- cated automatic test-pattern generator and with com- pression of the test response with a signature analysis register. the pc-based boundary-scan test card/soft- ware allows a user to quickly prototype a boundary- scan test setup. boundary-scan instructions the orca series boundary-scan circuitry is used for three mandatory ieee 1149.1 tests (extest, sam- ple/preload, bypass) and four orca -defined instructions. the 3-bit wide instruction register sup- ports the eight instructions listed in table 12. table 12. boundary-scan instructions the external test (extest) instruction allows the inter- connections between ics in a system to be tested for opens and stuck-at faults. if an extest instruction is performed for the system shown in figure 47, the con- nections between u1 and u2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether the same value is seen at the other device. this is deter- mined by shifting 2 bits of data for each pin (one for the output value and one for the 3-state value) through the bsr until each one aligns to the appropriate pin. then, based upon the value of the 3-state signal, either the i/o pad is driven to the value given in the bsr, or the bsr is updated with the input value from the i/o pad, which allows it to be shifted out tdo. the sample instruction is useful for system debug- ging and fault diagnosis by allowing the data at the fpgas i/os to be observed during normal operation. the data for all of the i/os is captured simultaneously into the bsr, allowing them to be shifted-out tdo to the test host. since each i/o buffer in the pics is bidi- rectional, two pieces of data are captured for each i/o pad: the value at the i/o pad and the value of the 3-state control signal. code instruction 000 extest 001 plc scan ring 1 010 ram write (ram_w) 011 reserved 100 sample/preload 101 plc scan ring 2 110 ram read (ram_r) 111 bypass
data sheet orca series 2 fpgas june 1999 56 lucent technologies inc. special function blocks (continued) there are four orca -defined instructions. the plc scan rings 1 and 2 (psr1, psr2) allow user-defined internal scan paths using the plc latches/ffs. the ram_write enable (ram_w) instruction allows the user to serially configure the fpga through tdi. the ram_read enable (ram_r) allows the user to read back ram contents on tdo after configuration. orca boundary-scan circuitry the orca series boundary-scan circuitry includes a test access port controller (tapc), instruction register (ir), boundary-scan register (bsr), and bypass regis- ter. it also includes circuitry to support the four pre- defined instructions. figure 49 shows a functional diagram of the boundary- scan circuitry that is implemented in the orca series. the input pins (tms, tck, and tdi) locations vary depending on the part, and the output pin is the dedi- cated tdo/rd_data output pad. test data in (tdi) is the serial input data. test mode select (tms) controls the boundary-scan test access port controller (tapc). test clock (tck) is the test clock on the board. the bsr is a series connection of boundary-scan cells (bscs) around the periphery of the ic. each i/o pad on the fpga, except for cclk, done, and the boundary- scan pins (tck, tdi, tms, and tdo), is included in the bsr. the first bsc in the bsr (connected to tdi) is located in the first pic i/o pad on the left of the top side of the fpga (pta pic). the bsr proceeds clock- wise around the top, right, bottom, and left sides of the array. the last bsc in the bsr (connected to tdo) is located on the top of the left side of the array (pla3). the bypass instruction uses a single ff which resyn- chronizes test data that is not part of the current scan operation. in a bypass instruction, test data received on tdi is shifted out of the bypass register to tdo. since the bsr (which requires a two ff delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. the boundary-scan logic is enabled before and during configuration. after configuration, a configuration option determines whether or not boundary-scan logic is used. the 32-bit boundary-scan identification register con- tains the manufacturers id number, unique part num- ber, and version, but is not implemented in the orca series of fpgas. if boundary scan is not used, tms, tdi, and tck become user i/os, and tdo is 3-stated or used in the readback operation. 5-2840(c).r7 figure 49. orca series boundary-scan circuitry functional diagram tap controller boundary-scan register psr2 register (plcs) bypass register data mux instruction decoder instruction register m u x reset clock-ir shift-ir update-ir pur tdo select enable reset clock-dr shift-dr update-dr tdi data registers psr1 register (plcs) configuration register (ram_r, ram_w) i/o buffers v dd tms v dd tck v dd prgm v dd
lucent technologies inc. 57 data sheet june 1999 orca series 2 fpgas special function blocks (continued) orca series tap controller (tapc) the orca series tap controller (tapc) is a 1149.1 compatible test access port controller. the 16 jtag state assignments from the ieee 1149.1 specification are used. the tapc is controlled by tck and tms. the tapc states are used for loading the ir to allow three basic functions in testing: providing test stimuli (update-dr), test execution (run-test/idle), and obtaining test responses (capture-dr). the tapc allows the test host to shift in and out both instructions and test data/results. the inputs and outputs of the tapc are provided in the table below. the outputs are primarily the control signals to the instruction register and the data register. table 13. tap controller input/outputs the tapc generates control signals which allow cap- ture, shift, and update operations on the instruction and data registers. in the capture operation, data is loaded into the register. in the shift operation, the captured data is shifted out while new data is shifted in. in the update operation, either the instruction register is loaded for instruction decode, or the boundary-scan register is updated for control of outputs. the test host generates a test by providing input into the orca series tms input synchronous with tck. this sequences the tapc through states in order to perform the desired function on the instruction register or a data register. figure 50 provides a diagram of the state transitions for the tapc. the next state is deter- mined by the tms input value. 5-5370(f) figure 50. tap controller state transition diagram symbol i/o function tms i test mode select tck i test clock pur i powerup reset prgm i bscan reset treset o test logic reset select o select ir (high); select dr (low) enable o test data out enable capture-dr o capture/parallel load dr capture-ir o capture/parallel load ir shift-dr o shift data register shift-dr o shift instruction register update-dr o update/parallel load dr update-ir o update/parallel load ir select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 1 0 0 10 run-test/ idle 1 test-logic- reset select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 1 0 10 00 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 11 0
data sheet orca series 2 fpgas june 1999 58 lucent technologies inc. special function blocks (continued) boundary-scan cells figure 51 is a diagram of the boundary-scan cell (bsc) in the orca series pics. there are four bscs in each pic: one for each pad, except as noted above. the bscs are connected serially to form the bsr. the bsc controls the functionality of the in, out, and 3-state signals for each pad. the bsc allows the i/o to function in either the normal or test mode. normal mode is defined as when an out- put buffer receives input from the plc array and pro- vides output at the pad or when an input buffer provides input from the pad to the plc array. in the test mode, the bsc executes a boundary-scan operation, such as shifting in scan data from an upstream bsc in the bsr, providing test stimuli to the pad, capturing test data at the pad, etc. the primary functions of the bsc are shifting scan data serially in the bsr and observing input (p_in), output (p_out), and 3-state (p_ts) signals at the pads. the bsc consists of two circuits: the bidirectional data cell is used to access the input and output data, and the direction control cell is used to access the 3-state value. both cells consist of a flip-flop used to shift scan data which feeds a flip-flop to control the i/o buffer. the bidirectional data cell is connected serially to the direc- tion control cell to form a boundary-scan shift register. the tapc signals (capture, update, shiftn, treset, and tck) and the mode signal control the operation of the bsc. the bidirectional data cell is also controlled by the high out/low in (holi) signal generated by the direction control cell. when holi is low, the bidirec- tional data cell receives input buffer data into the bsc. when holi is high, the bsc is loaded with functional data from the plc. the mode signal is generated from the decode of the instruction register. when the mode signal is high (extest), the scan data is propagated to the output buffer. when the mode signal is low (bypass or sample), functional data from the fpgas internal logic is propagated to the output buffer. the boundary-scan description language (bsdl) is provided for each device in the orca series of fpgas. the bsdl is generated from a device profile, pinout, and other boundary-scan information. 5-2844(f).r4 figure 51. boundary-scan cell d q d q d q d q scan in p_out holi bidirectional data cell i/o buffer direction control cell mode update/tck scan out tck shiftn/capture p_ts p_in pad_in pad_ts pad_out 0 1 0 1 0 1 0 1 0 1
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 59 special function blocks (continued) fig.5.3(f) figure 52. instruction register scan timing diagram boundary-scan timing to ensure race-free operation, data changes on specific clock edges. the tms and tdi inputs are clocked in on the rising edge of tck, while changes on tdo occur on the falling edge of tck. in the execution of an extest instruction, parallel data is output from the bsr to the fpga pads on the falling edge of tck. the maximum fre- quency allowed for tck is 10 mhz. figure 52 shows timing waveforms for an instruction scan operation. the diagram shows the use of tms to sequence the tapc through states. the test host (or bsm) changes data on the falling edge of tck, and it is clocked into the dut on the rising edge. test-logic-reset run-test/idle select-dr-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir shift-ir exit1-ir update-ir run-test/idle select-ir-scan tck tms tdi
60 lucent technologies inc. data sheet orca series 2 fpgas june 1999 orca timing characteristics to define speed grades, the orca series part number designation (see table 54) uses a single-digit number to designate a speed grade. this number is not related to any single ac parameter. higher numbers indicate a faster set of timing parameters. the actual speed sort- ing is based on testing the delay in a path consisting of an input buffer, combinatorial delay through all plcs in a row, and an output buffer. other tests are then done to verify other delay parameters, such as routing delays, setup times to ffs, etc. the most accurate timing characteristics are reported by the timing analyzer in the orca foundry develop- ment system. a timing report provided by the develop- ment system after layout divides path delays into logic and routing delays. the timing analyzer can also pro- vide logic delays prior to layout. while this allows rout- ing budget estimates, there is wide variance in routing delays associated with different layouts. the logic timing parameters noted in the electrical characteristics section of this data sheet are the same as those in the design tools. in the pfu timing given in tables 3179, symbol names are generally a concate- nation of the pfu operating mode (as defined in table 3) and the parameter type. the wildcard charac- ter (*) is used in symbol names to indicate that the parameter applies to any sub-lut. the setup, hold, and propagation delay parameters, defined below, are designated in the symbol name by the set, hld, and del characters, respectively. the values given for the parameters are the same as those used during production testing and speed bin- ning of the devices. the junction temperature and sup- ply voltage used to characterize the devices are listed in the delay tables. actual delays at nominal tempera- ture and voltage for best-case processes can be much better than the values given. it should be noted that the junction temperature used in the tables is generally 85 c. the junction temperature for the fpga depends on the power dissipated by the device, the package thermal characteristics ( q ja ), and the ambient temperature, as calculated in the following equation and as discussed further in the package thermal characteristics section: t jmax = t amax + (p ? q ja ) c note : the user must determine this junction tempera- ture to see if the delays from orca foundry should be derated based on the following derat- ing tables. table 14a and 14b and provide approximate power supply and junction temperature derating for or2cxxa commercial and industrial devices. table 15a and 15b provides the same information for the or2txxa and or2txxb devices (both commercial and industrial). the delay values in this data sheet and reported by orca foundry are shown as 1.00 in the tables. the method for determining the maximum junction temper- ature is defined in the thermal characteristics section. taken cumulatively, the range of parameter values for best-case vs. worst-case processing, supply voltage, and junction temperature can approach 3 to 1. table 14a. derating for commercial devices (or2cxxa) table 14b. derating for industrial devices (or2cxxa) table 15a. derating for commercial/industrial devices (or2txxa) t j (c) power supply voltage 4.75 v 5.0 v 5.25 v 0 0.81 0.79 0.77 25 0.85 0.83 0.81 85 1.00 0.97 0.95 100 1.05 1.02 1.00 125 1.12 1.09 1.07 t j (c) power supply voltage 4.5 v 4.75 v 5.0 v 5.25 v 5.5 v C40 0.71 0.70 0.68 0.66 0.65 0 0.80 0.78 0.76 0.74 0.73 25 0.84 0.82 0.80 0.78 0.77 85 1.00 0.97 0.94 0.93 0.91 100 1.05 1.01 0.99 0.97 0.95 125 1.12 1.09 1.06 1.04 1.02 t j (c) power supply voltage 3.0 v 3.3 v 3.6 v C40 0.73 0.66 0.61 0 0.82 0.73 0.68 25 0.87 0.78 0.72 85 1.00 0.90 0.83 100 1.04 0.94 0.87 125 1.10 1.00 0.92
lucent technologies inc. 61 data sheet june 1999 orca series 2 fpgas orca timing characteristics (continued) table 15b. derating for commercial/industrial devices (or2txxb) note: the derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. since the routing delay derates at a higher rate than the logic delay, paths with more than 66% routing delay will derate at a higher rate than shown in the table. the approximate derating values vs. temperature are 0.26% per c for logic delay and 0.45% per c for routing delay. the approximate derating values vs. voltage are 0.13% per mv for both logic and routing delays at 25 c. in addition to supply voltage, process variation, and operating temperature, circuit and process improve- ments of the orca series fpgas over time will result in significant improvement of the actual performance over those listed for a speed grade. even though lower speed grades may still be available, the distribution of yield to timing parameters may be several speed bins higher than that designated on a product brand. design practices need to consider best-case timing parame- ters (e.g., delays = 0), as well as worst-case timing. the routing delays are a function of fan-out and the capacitance associated with the cips and metal inter- connect in the path. the number of logic elements that can be driven (or fan-out) by pfus is unlimited, although the delay to reach a valid logic level can exceed timing requirements. it is difficult to make accu- rate routing delay estimates prior to design compilation based on fan-out. this is because the cae software may delete redundant logic inserted by the designer to reduce fan-out, and/or it may also automatically reduce fan-out by net splitting. the waveform test points are given in the measure- ment conditions section of this data sheet. the timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and the val- ues they reflect are described below. n propagation delay the time between the specified reference points. the delays provided are the worst case of the tphh and tpll delays for noninverting func- tions, tplh and tphl for inverting functions, and tphz and tplz for 3-state enable. n setup time the interval immediately preceding the transition of a clock or latch enable signal, during which the data must be stable to ensure it is recog- nized as the intended value. n hold time the interval immediately following the transition of a clock or latch enable signal, during which the data must be held stable to ensure it is rec- ognized as the intended value. n 3-state enable the time from when a ts[3:0] signal becomes active and the output pad reaches the high- impedance state. estimating power dissipation or2cxxa the total operating power dissipated is estimated by summing the standby (i ddsb ), internal, and external power dissipated. the internal and external power is the power consumed in the plcs and pics, respec- tively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = s p plc + s p pic the internal operating power is made up of two parts: clock generation and pfu output power. the pfu out- put power can be estimated based upon the number of pfu outputs switching when driving an average fan-out of two: p pfu = 0.16 mw/mhz for each pfu output that switches, 0.16 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. the power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/clock branch row or column, the clock power dis- sipated in each pfu that uses this particular clock, and the power from the subset of those pfus that is config- ured in either of the two synchronous modes (sspm or sdpm). therefore, the clock power can be calculated for the four parts using the following equations: or2c04a clock power p = [0.62 mw/mhz + (0.22 mw/mhz C branch) (# branches) + (0.022 mw/mhz C pfu) (# pfus) + (0.006 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2c04a clock power ? 3.9 mw/mhz. t j (c) power supply voltage 3.0 v 3.15 v 3.3 v 3.45 v 3.6 v C40 0.81 0.78 0.76 0.74 0.73 0 0.86 0.83 0.80 0.77 0.76 25 0.9 0.87 0.83 0.8 0.78 85 1.0 0.95 0.93 0.88 0.86 100 1.02 0.98 0.95 0.91 0.88 125 1.06 1.03 0.98 0.95 0.92
62 lucent technologies inc. data sheet orca series 2 fpgas june 1999 estimating power dissipation (continued) or2c06a clock power p = [0.63 mw/mhz + (0.25 mw/mhz C branch) (# branches) + (0.022 mw/mhz C pfu) (# pfus) + (0.006 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2c06a clock power ? 5.3 mw/mhz. or2c08a clock power p = [0.65 mw/mhz + (0.29 mw/mhz C branch) (# branches) + (0.022 mw/mhz C pfu) (# pfus) + (0.006 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2c08a clock power ? 6.6 mw/mhz. or2c10a clock power p = [0.66 mw/mhz + (0.32 mw/mhz C branch) (# branches) + (0.022 mw/mhz C pfu) (# pfus) + (0.006 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2c10a clock power ? 8.6 mw/mhz. or2c12a clock power p = [0.68 mw/mhz + (0.35 mw/mhz C branch) (# branches) + (0.022 mw/mhz C pfu) (# pfus) + (0.006 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2c12a clock power ? 10.5 mw/mhz. or2c15a clock power p = [0.69 mw/mhz + (0.38 mw/mhz C branch) (# branches) + (0.022 mw/mhz C pfu) (# pfus) + (0.006 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2c15a clock power ? 12.7 mw/mhz. or2c26a clock power p = [0.73 mw/mhz + (0.44 mw/mhz C branch) (# branches) + (0.022 mw/mhz C pfu) (# pfus) + (0.006 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2c26a clock power ? 17.8 mw/mhz. or2c40a clock power p = [0.77 mw/mhz + (0.53 mw/mhz C branch) (# branches) + (0.022 mw/mhz C pfu) (# pfus) + (0.006 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2c40a clock power ? 26.6 mw/mhz. the power dissipated in a pic is the sum of the power dissipated in the four i/os in the pic. this consists of power dissipated by inputs and ac power dissipated by outputs. the power dissipated in each i/o depends on whether it is configured as an input, output, or input/ output. if an i/o is operating as an output, then there is a power dissipation component for p in , as well as p out . this is because the output feeds back to the input. the power dissipated by a ttl input buffer is estimated as: p ttl = 2.2 mw + 0.17 mw/mhz the power dissipated by an input buffer is estimated as: p cmos = 0.17 mw/mhz the ac power dissipation from an output or bidirec- tional is estimated by the following: p out = (c l + 8.8 pf) x v dd 2 x f watts where the unit for c l is farads, and the unit for f is hz. as an example of estimating power dissipation, suppose that a fully utilized or2c15a has an average of three outputs for each of the 400 pfus, that all 20 clock branches are used, that 150 of the 400 pfus have ffs clocked at 40 mhz (16 of which are operating in a synchronous memory mode), and that the pfu outputs have an average activity factor of 20%. twenty ttl-configured inputs, 20 cmos-configured inputs, 32 outputs driving 30 pf loads, and 16 bidirec- tional i/os driving 50 pf loads are also generated from the 40 mhz clock with an average activity factor of 20%. the worst-case (v dd = 5.25 v) power dissipation is estimated as follows: p pfu = 400 x 3 (0.16 mw/mhz x 20 mhz x 20%) = 768 mw
lucent technologies inc. 63 data sheet june 1999 orca series 2 fpgas estimating power dissipation (continued) p clk = [0.69 mw/mhz + (0.38 mw/mhz C branch) (20 branches) + (0.022 mw/mhz C pfu) (150 pfus) + (0.006 mw/mhz C smem_pfu) (16 smem_pfus)] [40 mhz] = 427 mw p ttl = 20 x [2.2 mw + (0.17 mw/mhz x 20 mhz x 20%)] = 57 mw p cmos = 20 x [0.17 mw x 20 mhz x 20%] = 13 mw p out = 30 x [(30 pf + 8.8 pf) x (5.25) 2 x 20 mhz x 20%] =128 mw p bid = 16 x [(50 pf + 8.8 pf) x (5.25) 2 x 20 mhz x 20%] = 104 mw total = 1.50 w or2txxa the total operating power dissipated is estimated by summing the standby (i ddsb ), internal, and external power dissipated. the internal and external power is the power consumed in the plcs and pics, respec- tively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = s p plc + s p pic the internal operating power is made up of two parts: clock generation and pfu output power. the pfu out- put power can be estimated based upon the number of pfu outputs switching when driving an average fan-out of two: p pfu = 0.08 mw/mhz for each pfu output that switches, 0.08 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. the power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/clock branch row or column, the clock power dis- sipated in each pfu that uses this particular clock, and the power from the subset of those pfus that is config- ured in either of the two synchronous modes (sspm or sdpm). therefore, the clock power can be calculated for the four parts using the following equations: or2t04a clock power p = [0.29 mw/mhz + (0.10 mw/mhz C branch) (# branches) + (0.01 mw/mhz C pfu) (# pfus) + (0.003 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t04a clock power ? 1.8 mw/mhz. or2t06a clock power p = [0.30 mw/mhz + (0.11 mw/mhz C branch) (# branches) + (0.01 mw/mhz C pfu) (# pfus) + (0.003 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t06a clock power ? 2.4 mw/mhz. or2t08a clock power p = [0.31 mw/mhz + (0.12 mw/mhz C branch) (# branches) + (0.01 mw/mhz C pfu) (# pfus) + (0.003 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t08a clock power ? 3.2 mw/mhz. or2t10a clock power p = [0.32 mw/mhz + (0.14 mw/mhz C branch) (# branches) + (0.01 mw/mhz C pfu) (# pfus) + (0.003 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t10a clock power ? 4.0 mw/mhz. or2t12a clock power p = [0.33 mw/mhz + (0.15 mw/mhz C branch) (# branches) + (0.01 mw/mhz C pfu) (# pfus) + (0.003 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t12a clock power ? 4.9 mw/mhz.
64 lucent technologies inc. data sheet orca series 2 fpgas june 1999 estimating power dissipation (continued) or2t15a clock power p = [0.34 mw/mhz + (0.17 mw/mhz C branch) (# branches) + (0.01 mw/mhz C pfu) (# pfus) + (0.003 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t15a clock power ? 5.9 mw/mhz. or2t26a clock power p = [0.35 mw/mhz + (0.19 mw/mhz C branch) (# branches) + (0.01 mw/mhz C pfu) (# pfus) + (0.003 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t26a clock power ? 8.3 mw/mhz. or2t40a clock power p = [0.37 mw/mhz + (0.23 mw/mhz C branch) (# branches) + (0.01 mw/mhz C pfu) (# pfus) + (0.003 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t40a clock power ? 12.4 mw/mhz. the power dissipated in a pic is the sum of the power dissipated in the four i/os in the pic. this consists of power dissipated by inputs and ac power dissipated by outputs. the power dissipated in each i/o depends on whether it is configured as an input, output, or input/ output. if an i/o is operating as an output, then there is a power dissipation component for p in , as well as p out . this is because the output feeds back to the input. the power dissipated by an input buffer (v ih = v dd C 0.3 v or higher) is estimated as: p in = 0.09 mw/mhz the 5 v tolerant input buffer feature dissipates addi- tional dc power. the dc power, p tol , is always dissi- pated for the or2txxa, regardless of the number of 5 v tolerant input buffers used when the v dd 5 pins are connected to a 5 v supply as shown in table 16. this power is not dissipated when the v dd 5 pins are con- nected to the 3.3 v supply. table 16. dc power for 5 v tolerant i/os for or2txxa deviced the ac power dissipation from an output or bidirec- tional is estimated by the following: p out = (c l + 8.8 pf) x v dd 2 x f watts where the unit for c l is farads, and the unit for f is hz. as an example of estimating power dissipation, suppose that a fully utilized or2t15a has an average of three outputs for each of the 400 pfus, that all 20 clock branches are used, that 150 of the 400 pfus have ffs clocked at 40 mhz (16 of which are operating in a synchronous memory mode), and that the pfu outputs have an average activity factor of 20%. twenty inputs, 32 outputs driving 30 pf loads, and 16 bidirectional i/os driving 50 pf loads are also gen- erated from the 40 mhz clock with an average activity factor of 20%. the worst-case (v dd = 3.6 v) power dis- sipation is estimated as follows: p pfu = 400 x 3 (0.08 mw/mhz x 20 mhz x 20%) = 384 mw p clk = [0.34 mw/mhz + (0.17 mw/mhz C branch) (20 branches) + (0.01 mw/mhz C pfu) (150 pfus) + (0.003 mw/mhz C smem_pfu) (16 smem_pfus)] [40 mhz] = 212 mw p in = 20 x [0.09 mw/mhz x 20 mhz x 20%] = 7 mw p tol = 3.4 mw p out = 30 x [(30 pf + 8.8 pf) x (3.6) 2 x 20 mhz x 20%] = 60 mw p bid = 16 x [(50 pf + 8.8 pf) x (3.6) 2 x 20 mhz x 20%] = 49 mw total = 0.72 w device p tol (v dd 5 = 5.25 v) 2t04a 1.7 mw 2t06a 2.0 mw 2t08a 2.4 mw 2t10a 2.7 mw 2t12a 3.0 mw 2t15a 3.4 mw 2t26a 4.0 mw 2t40a 5.0 mw
lucent technologies inc. 65 data sheet june 1999 orca series 2 fpgas estimating power dissipation (continued) or2t15b and or2t40b the total operating power dissipated is estimated by summing the standby (i ddsb ), internal, and external power dissipated. the internal and external power is the power consumed in the plcs and pics, respec- tively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = s p plc + s p pic the internal operating power is made up of two parts: clock generation and pfu output power. the pfu out- put power can be estimated based upon the number of pfu outputs switching when driving an average fan-out of two: p pfu = 0.08 mw/mhz for each pfu output that switches, 0.08 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. the power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/clock branch row or column, the clock power dis- sipated in each pfu that uses this particular clock, and the power from the subset of those pfus that is config- ured in either of the two synchronous modes (sspm or sdpm). therefore, the clock power can be calculated for the four parts using the following equations: or2t15b clock power p = [0.30 mw/mhz + (0.85 mw/mhz C branch) (# branches) + (0.008 mw/mhz C pfu) (# pfus) + (0.002 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t15b clock power ? 3.9 mw/mhz. or2t40b clock power p = [0.42 mw/mhz + (0.118 mw/mhz C branch) (# branches) + (0.008 mw/mhz C pfu) (# pfus) + (0.002 mw/mhz C smem_pfu) (# smem_pfus)] fclk for a quick estimate, the worst-case (typical circuit) or2t40b clock power ? 5.5 mw/mhz. the power dissipated in a pic is the sum of the power dissipated in the four i/os in the pic. this consists of power dissipated by inputs and ac power dissipated by outputs. the power dissipated in each i/o depends on whether it is configured as an input, output, or input/ output. if an i/o is operating as an output, then there is a power dissipation component for p in , as well as p out . this is because the output feeds back to the input. the power dissipated by an input buffer (v ih = v dd C 0.3 v or higher) is estimated as: p in = 0.033 mw/mhz the or2txxb 5 v tolerant input buffer feature does not dissipate additional dc power. the ac power dissipation from an output or bidirec- tional is estimated by the following: p out = (c l + 8.8 pf) x v dd 2 x f watts where the unit for c l is farads, and the unit for f is hz. as an example of estimating power dissipation, suppose that a fully utilized or2t15b has an average of three outputs for each of the 400 pfus, that all 20 clock branches are used, that 150 of the 400 pfus have ffs clocked at 40 mhz (16 of which are operating in a synchronous memory mode), and that the pfu outputs have an average activity factor of 20%. twenty inputs, 32 outputs driving 30 pf loads, and 16 bidirectional i/os driving 50 pf loads are also gen- erated from the 40 mhz clock with an average activity factor of 20%. the worst-case (v dd = 3.6 v) power dis- sipation is estimated as follows: p pfu = 400 x 3 (0.08 mw/mhz x 20 mhz x 20%) = 384 mw p clk = [0.30 mw/mhz + (0.085 mw/mhz C branch) (20 branches) + (0.008 mw/mhz C pfu) (150 pfus) + (0.002 mw/mhz C smem_pfu) (16 smem_pfus)] [40 mhz] = 129 mw p in = 20 x [0.033 mw/mhz x 20 mhz x 20%] = 3 mw p tol = 3.4 mw p out = 30 x [(30 pf + 8.8 pf) x (3.6) 2 x 20 mhz x 20%] = 60 mw p bid = 16 x [(50 pf + 8.8 pf) x (3.6) 2 x 20 mhz x 20%] = 49 mw total = 0.72 w
data sheet orca series 2 fpgas june 1999 66 lucent technologies inc. pin information pin descriptions this section describes the pins found on the series 2 fpgas. any pin not described in this table is a user-program- mable i/o. during configuration, the user-programmable i/os are 3-stated with an internal pull-up resistor enabled. table 17. pin descriptions symbol i/o description dedicated pins v dd positive power supply. gnd ground supply. i/o-v dd 5 5 v tolerant select. (for 2txxa only.) all v dd 5 pins must be tied to either the 5 v power supply if 5 v tolerant i/o buffers are to be used, or to the 3.3 v power supply (v dd ) if they are not. for 2cxxa and 2txxb devices, these pins are user-programmable i/os. reset i during configuration, reset forces the restart of configuration and a pull-up is enabled. after configuration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i in the master and asynchronous peripheral modes, cclk is an output which strobes configuration data in. in the slave or synchronous peripheral mode, cclk is input syn- chronous with the data on din or d[7:0]. done i/o done is a bidirectional pin with an optional pull-up resistor. as an active-high, open- drain output, a high-level on this signal indicates that configuration is complete. as an input, a low level on done delays fpga start-up after configuration*. prgm iprgm is an active-low input that forces the restart of configuration and resets the boundary-scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pullup. during configuration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after configuration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the configuration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides configu- ration data out. if used in boundary scan, tdo is test data out. special-purpose pins (become user i/o after configuration) rdy/rclk o during configuration in peripheral mode, rdy indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. after configuration, the pin is a user-programmable i/o*. during the master parallel configuration mode rclk, which is a read output signal to an external memory. this output is not normally used. after configuration, this pin is a user- programmable i/o pin*. din i during slave serial or master serial configuration modes, din accepts serial configura- tion data synchronous with cclk. during parallel configuration modes, din is the d0 input. during configuration, a pull-up is enabled, and after configuration, this pin is a user-programmable i/o pin*. * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration p ins (and the acti- vation of all user i/os) is controlled by a second set of options.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 67 special-purpose pins special-purpose pins (become user i/o after configuration) (continued) m0, m1, m2 i during powerup and initialization, m0m2 are used to select the configuration mode with their values latched on the rising edge of init . see table 7 for the configuration modes. during configuration, a pull-up is enabled, and after configuration, the pins are user-programmable i/o*. m3 i during powerup and initialization, m3 is used to select the speed of the internal oscilla- tor during configuration, with its value latched on the rising edge of init . when m3 is low, the oscillator frequency is 10 mhz. when m3 is high, the oscillator is 1.25 mhz. during configuration, a pull-up is enabled, and after configuration, this pin is a user-pro- grammable i/o pin*. tdi, tck, tms i if boundary scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary scan is not selected, all boundary-scan functions are inhibited once configuration is complete, and these pins are user-programmable i/o pins. even if boundary scan is not used, either tck or tms must be held at logic 1 during configura- tion. each pin has a pull-up enabled during configuration*. hdc o high during configuration is output high until configuration is complete. it is used as a control output indicating that configuration is not complete. after configuration, this pin is a user-programmable i/o pin*. ldc o low during configuration is output low until configuration is complete. it is used as a control output indicating that configuration is not complete. after configuration, this pin is a user-programmable i/o pin*. init i/o init is a bidirectional signal before and during configuration. during configuration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of configuration. after configuration, the pin is a user-programmable i/o pin*. cs0 , cs1, wr , rd ics0 , cs1, wr , rd are used in the asynchronous peripheral configuration modes. the fpga is selected when cs0 is low and cs1 is high. when selected, a low on the write strobe, wr , loads the data on d[7:0] inputs into an internal data buffer. wr , cs0 , and cs1 are also used as chip selects in the slave parallel mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe overrides. during configuration, a pull-up is enabled, and after con- figuration, the pins are user-programmable i/o pins*. a[17:0] o during master parallel configuration mode, a[17:0] address the configuration eprom. during configuration, a pull-up is enabled, and after configuration, the pins are user- programmable i/o pins*. d[7:0] i during master parallel, peripheral, and slave parallel configuration modes, d[7:0] receive configuration data and each pin has a pull-up enabled. after configuration, the pins are user-programmable i/o pins*. dout o during configuration, dout is the serial data output that can drive the din of daisy- chained slave lca devices. data out on dout changes on the falling edge of cclk. after configuration, dout is a user-programmable i/o pin*. table 17. pin descriptions (continued) symbol i/o description * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration p ins (and the acti- vation of all user i/os) is controlled by a second set of options. pin information (continued)
data sheet orca series 2 fpgas june 1999 68 lucent technologies inc. pin information (continued) package compatibility the package pinouts are consistent across orca series fpgas with the following exception: some user i/o pins that do not have any special functions will be converted to v dd 5 pins for the or2txxa series . if the designer does not use these pins for the or2cxxa and or2txxb series, then pinout compati- bility will be maintained between the orca or2cxxa, or2txxa, and or2txxb series of fpgas. note that they must be connected to a power supply for the or2txxa series. package pinouts being consistent across all orca series fpgas enables a designer to select a package based on i/o requirements and change the fpga with- out laying out the printed-circuit board again. the change might be to a larger fpga if additional func- tionality is needed, or it might be to a smaller fpga to decrease unit cost. table 18a provides the number of user i/os available for the orca or2cxxa and or2txxb series fpgas for each available package, and table 18b provides the number of user i/os available in the orca or2txxa series. it should be noted that the number of user i/os available for the or2txxa series is reduced from the equivalent or2cxxa devices by the number of required v dd 5 pins, as shown in table 18b. the pins that are converted from user i/o to v dd 5 are denoted as i/o-v dd 5 in the pin information tables (table 19 through 28). each package has six dedicated configu- ration pins. table 19table 28. provide the package pin and pin function for the orca series 2 fpgas and packages. the bond pad name is identified in the pic nomencla- ture used in the orca foundry design editor. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). when a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device pad column for the fpga. the tables provide no information on unused pads. * 432 ebga not available for or2t15b table 18a. orca or2cxxa and or2txxb series fpga i/os summary device 84-pin plcc 100-pin tqfp 144-pin tqfp 160-pin qfp 208-pin sqfp/ sqfp2 240-pin sqfp/ sqfp2 256-pin pbga 304-pin sqfp/ sqfp2 352-pin pbga 432-pin ebga or2c04a user i/os 64 77 114 130 160 v dd /v ss 14 17 24 24 31 or2c06a user i/os 64 77 114 130 171 192 192 v dd /v ss 14 17 24 24 31 42 26 or2c08a user i/os 64 130 171 192 221 v dd /v ss 14 24 31 40 26 or2c10a user i/os 64 130 171 192 221 256 v dd /v ss 14 24 31 40 26 48 or2c12a user i/os 64 171 192 223 252 288 v dd /v ss 1431 42264648 or2c15a/or2t15b user i/os 64 171 192 223 252 298 320* v dd /v ss 1431 4226464884 or2c26a user i/os 171 192 252 298 342 v dd /v ss 31 42 46 48 84 or2c40a/or2t40b user i/os 171 192 252 342 v dd /v ss 31 42 46 84
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 69 pin information (continued) table 18b. orca or2txxa series fpga i/os summary device 84-pin plcc 100-pin tqfp 144-pin tqfp 160-pin qfp 208-pin sqfp/ sqfp2 240-pin sqfp/ sqfp2 256-pin pbga 352-pin pbga 432-pin ebga or2t04a user i/os 62 74 110 126 152 v dd /v ss 14 17 24 24 31 v dd 523448 or2t06a user i/os 62 74 110 126 163 184 182 v dd /v ss 14 17 24 24 31 42 26 v dd 523448810 or2t08a user i/os 62 126 163 184 209 v dd /v ss 14 24 31 40 26 v dd 5248812 or2t10a user i/os 62 126 163 184 209 244 v dd /v ss 14 24 31 40 26 48 v dd 524881212 or2t12a user i/os 62 163 184 211 276 v dd /v ss 14 31 42 26 48 v dd 52881212 or2t15a user i/os 62 163 184 211 286 307 v dd /v ss 14 31 42 26 48 84 v dd 5288121212 or2t26a user i/os 163 184 286 326 v dd /v ss 31 42 48 84 v dd 5 8 8 12 16 or2t40a user i/os 163 184 286 326 v dd /v ss 31 42 48 84 v dd 5 8 8 12 16
data sheet orca series 2 fpgas june 1999 70 lucent technologies inc. pin information (continued) compatibility with series 3 fpgas pinouts for the or2cxxa, or2txxa, and or2txxb devices will be consistent with the series 3 fpgas for all devices offered in the same packages. this includes the following pins: v dd , v ss , v dd 5 (or3c/txxx series only), and all configuration pins. identical to the or2txxb devices, series 3 devices provide 5 v tolerant i/os without a dedicated v dd 5 supply the following restrictions apply: 1. there are two configuration modes supported in the or2c/txxa series that are not supported in the series 3 fpgas series: master parallel down and synchronous peripheral modes. the series 3 fpgas have two new microprocessor interface (mpi) configuration modes that are unavailable in the series 2. 2. there are 4 pinsone per each device sidethat are user i/o in the or2c/txxa series which can only be used as fast dedicated clocks or global inputs in the series 3 series. these pins are also used to drive the express- clk to the i/o ffs on their given side of the device. these four middle expressclk pins should not be used to connect to a programmable clock manager (pcm). a corner expressclk input should be used instead (see note below). see table 18c for a list of these pins in each package. 3. there are two other pins that are user i/o in both the series 2 and series 3 series but also have optional added functionality in the series 3 series. each of these pins drives the expressclks on two sides of the device. they also have fast connectivity to the programmable clock manager (pcm). see table 18c for a preliminary list of these pins in each package. note: the eckr, eckl, eckt, and eckb pins drive the expressclk on their given edge of the device, while i/oseckll and i/oseckur drive an expressclk on two edges of the device and provide connectivity to the programmable clock manager. table 18c. series 3 expressclk pins pin name/ package 208-pin sqfp2 240-pin sqfp2 256-pin pbga 352-pin pbga 432-pin ebga 600-pin ebga eckl 22 26 k3 n2 r29 u33 eckb 80 91 w11 ae14 ah16 am18 eckr 131 152 k18 n23 t2 v2 eckt 178 207 b11 b14 c15 c17 i/oseckll 49 56 w1 ab4 ag29 ak34 i/oseckur 159 184 a19 a25 d5 d5
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 71 pin information (continued) table 19. or2c/2t04a, or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, and or2c/2t15a 84-pin plcc pinout pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a pad function 1v ss v ss v ss v ss v ss v ss v ss 2 pt5a pt6a pt7a pt8a pt9a pt10a i/o-d2 3v ss v ss v ss v ss v ss v ss v ss 4 pt4d pt5d pt6d pt7d pt8d pt9d i/o-d1 5 pt4a pt5a pt6a pt7a pt8a pt9a i/o-d0/din 6 pt3a pt4a pt5a pt6a pt7a pt8a i/o-dout 7 pt2d pt3d pt4d pt5d pt6d pt7d i/o-v dd 5 8 pt2a pt3a pt4a pt4a pt5a pt6a i/o-tdi 9 pt1d pt2a pt3a pt3a pt3a pt4a i/o-tms 10 pt1a pt1a pt1a pt1a pt1a pt1a i/o-tck 11 rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo 12 v dd v dd v dd v dd v dd v dd v dd 13 v ss v ss v ss v ss v ss v ss v ss 14 pl1c pl1a pl2d pl2d pl2d pl2d i/o-a0 15 pl1a pl2a pl3a pl3a pl4a pl5a i/o-a1 16 pl2d pl3d pl4d pl4a pl5a pl6a i/o-a2 17 pl2a pl3a pl4a pl5a pl6a pl7a i/o-a3 18 pl3a pl4a pl5a pl6a pl7a pl8a i/o-a4 19 pl4d pl5d pl6d pl7d pl8d pl9d i/o-a5 20 pl4a pl5a pl6a pl7a pl8a pl9a i/o-a6 21 pl5a pl6a pl7a pl8a pl9a pl10a i/o-a7 22 v dd v dd v dd v dd v dd v dd v dd 23 pl6a pl7a pl8a pl9a pl10a pl11a i/o-a8 24 v ss v ss v ss v ss v ss v ss v ss 25 pl7d pl8d pl9d pl10d pl11d pl12d i/o-a9 26 pl7a pl8a pl9a pl10a pl11a pl12a i/o-a10 27 pl8a pl9a pl10a pl11a pl12a pl13a i/o-a11 28 pl9d pl10d pl11d pl12d pl13d pl14d i/o-a12 29 pl9a pl10a pl11a pl13d pl14b pl15b i/o-a13 30 pl10d pl11a pl12a pl14c pl16d pl17d i/o-a14 31 pl10a pl12a pl14a pl16a pl18a pl20a i/o-a15 32 cclk cclk cclk cclk cclk cclk cclk 33 v dd v dd v dd v dd v dd v dd v dd 34 v ss v ss v ss v ss v ss v ss v ss 35 pb1a pb1a pb1a pb1a pb1a pb1a i/o-a16 36 pb1d pb2a pb3a pb3b pb3d pb4d i/o-a17 37 pb2a pb3a pb3d pb4d pb5b pb6b i/o 38 pb2d pb3d pb4d pb5d pb6d pb7d i/o 39 pb3a pb4a pb5a pb6a pb7a pb8a i/o 40 pb4a pb5a pb6a pb7a pb8a pb9a i/o 41 pb4d pb5d pb6d pb7d pb8d pb9d i/o 42 pb5a pb6a pb7a pb8a pb9a pb10a i/o note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 72 lucent technologies inc. 43 v ss v ss v ss v ss v ss v ss v ss 44 pb6a pb7a pb8a pb9a pb10a pb11a i/o 45 v ss v ss v ss v ss v ss v ss v ss 46 pb7a pb8a pb9a pb10a pb11a pb12a i/o-v dd 5 47 pb7d pb8d pb9d pb10d pb11d pb12d i/o 48 pb8a pb9a pb10a pb11a pb12a pb13a i/o-hdc 49 pb9a pb10a pb11a pb12a pb13a pb14a i/o- ldc 50 pb9d pb10d pb11d pb13a pb13d pb14d i/o 51 pb10a pb11a pb12c pb13d pb15a pb16a i/o- init 52 pb10d pb12a pb13d pb15d pb18d pb20d i/o 53 done done done done done done done 54 reset reset reset reset reset reset reset 55 prgm prgm prgm prgm prgm prgm prgm 56 pr10a pr12a pr14a pr16a pr18a pr20a i/o-m0 57 pr10d pr11a pr12a pr14a pr16a pr17a i/o 58 pr9a pr10a pr11a pr13b pr15d pr16d i/o-m1 59 pr9d pr10d pr11d pr12b pr13a pr14a i/o 60 pr8a pr9a pr10a pr11a pr12a pr13a i/o-m2 61 pr7a pr8a pr9a pr10a pr11a pr12a i/o-m3 62 pr7d pr8d pr9d pr10d pr11d pr12d i/o 63 pr6a pr7a pr8d pr9d pr10a pr11a i/o 64 v dd v dd v dd v dd v dd v dd v dd 65 pr5a pr6a pr7a pr8a pr9a pr10a i/o 66 v ss v ss v ss v ss v ss v ss v ss 67 pr4a pr5a pr6a pr7a pr8a pr9a i/o 68 pr4d pr5d pr6d pr7d pr8d pr9d i/o 69 pr3a pr4a pr5a pr6a pr7a pr8a i/o-cs1 70 pr2a pr3a pr4a pr5a pr6a pr7a i/o- cs0 71 pr2d pr3d pr4d pr4d pr5d pr6d i/o 72 pr1a pr2a pr3a pr3a pr4a pr5a i/o- rd 73 pr1d pr1a pr2a pr2a pr2a pr3a i/o- wr 74 rd_cfg rd_cfg rd_cfg rd_cfg rd_cfg rd_cfg rd_cfg 75 v dd v dd v dd v dd v dd v dd v dd 76 v ss v ss v ss v ss v ss v ss v ss 77 pt10c pt12a pt13d pt15d pt17d pt19a i/o-rdy/rclk 78 pt9d pt11a pt12c pt13d pt15d pt16d i/o-d7 79 pt9c pt10d pt11d pt13a pt14d pt15d i/o 80 pt9a pt10a pt11b pt12b pt13b pt14b i/o-d6 81 pt8a pt9a pt10a pt11a pt12a pt13a i/o-d5 82 pt7d pt8d pt9d pt10d pt11d pt12d i/o 83 pt7a pt8a pt9a pt10a pt11a pt12a i/o-d4 84 pt6a pt7a pt8a pt9a pt10a pt11a i/o-d3 pin information (continued) table 19. or2c/2t04a, or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, and or2c/2t15a 84-pin plcc pinout (continued) pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a pad function note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 73 pin information (continued) table 20. or2c/2t04a and or2c/2t06a 100-pin tqfp pinout pin 2c/2t04a pad 2c/2t06a pad function pin 2c/2t04a pad 2c/2t06a pad function 1v dd v dd v dd 43 pb8c pb9c i/o 2v ss v ss v ss 44 pb8d pb9d i/o 3 pl1c pl1a i/o-a0 45 pb9a pb10a i/o- ldc 4 pl1a pl2a i/o-a1 46 pb9d pb10d i/o 5 pl2d pl3d i/o-a2 47 pb10a pb11a i/o- init 6 pl2a pl3a i/o-a3 48 pb10d pb12a i/o 7 pl3d pl4d i/o 49 done done done 8 pl3a pl4a i/o-a4 50 v dd v dd v dd 9 pl4d pl5d i/o-a5 51 reset reset reset 10 pl4a pl5a i/o-a6 52 prgm prgm prgm 11 pl5d pl6d i/o 53 pr10a pr12a i/o-m0 12 pl5a pl6a i/o-a7 54 pr10d pr11a i/o 13 v dd v dd v dd 55 pr9a pr10a i/o-m1 14 pl6a pl7a i/o-a8 56 pr9d pr10d i/o 15 v ss v ss v ss 57 pr8a pr9a i/o-m2 16 pl7d pl8d i/o-a9 58 pr8d pr9d i/o 17 pl7a pl8a i/o-a10 59 pr7a pr8a i/o-m3 18 pl8a pl9a i/o-a11 60 pr7d pr8d i/o 19 pl9d pl10d i/o-a12 61 v ss v ss v ss 20 pl9c pl10c i/o 62 pr6a pr7a i/o 21 pl9a pl10a i/o-a13 63 v dd v dd v dd 22 pl10d pl11a i/o-a14 64 pr5a pr6a i/o 23 pl10a pl12a i/o-a15 65 v ss v ss v ss 24 v ss v ss v ss 66 pr4a pr5a i/o-v dd 5 25 cclk cclk cclk 67 pr4d pr5d i/o 26 v dd v dd v dd 68 pr3a pr4a i/o-cs1 27 v ss v ss v ss 69 pr3d pr4d i/o 28 pb1a pb1a i/o-a16 70 pr2a pr3a i/o- cs0 29 pb1c pb1d i/o 71 pr2d pr3d i/o 30 pb1d pb2a i/o-a17 72 pr1a pr2a i/o- rd 31 pb2a pb3a i/o 73 pr1c pr2d i/o 32 pb2d pb3d i/o 74 pr1d pr1a i/o- wr 33 pb3a pb4a i/o 75 rd_cfg rd_cfg rd_cfg 34 pb4a pb5a i/o 76 v dd v dd v dd 35 pb4d pb5d i/o 77 v ss v ss v ss 36 pb5a pb6a i/o 78 pt10c pt12a i/o-rdy/rclk 37 v ss v ss v ss 79 pt9d pt11a i/o-d7 38 pb6a pb7a i/o 80 pt9c pt10d i/o 39 v ss v ss v ss 81 pt9a pt10a i/o-d6 40 pb7a pb8a i/o-v dd 582pt8d pt9d i/o 41 pb7d pb8d i/o 83 pt8a pt9a i/o-d5 42 pb8a pb9a i/o-hdc 84 pt7d pt8d i/o note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 74 lucent technologies inc. pin 2c/2t04a pad 2c/2t06a pad function pin 2c/2t04a pad 2c/2t06a pad function 85 pt7a pt8a i/o-d4 93 pt3d pt4d i/o 86 pt6d pt7d i/o 94 pt3a pt4a i/o-dout 87 pt6a pt7a i/o-d3 95 pt2d pt3d i/o-v dd 5 88 v ss v ss v ss 96 pt2a pt3a i/o-tdi 89 pt5a pt6a i/o-d2 97 pt1d pt2a i/o-tms 90 v ss v ss v ss 98 pt1c pt1d i/o 91 pt4d pt5d i/o-d1 99 pt1a pt1a i/o-tck 92 pt4a pt5a i/o-d0/din 100 rd_data/ tdo rd_data/tdo rd_data/tdo note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. pin information (continued) table 20. or2c/2t04a and or2c/2t06a 100-pin tqfp pinout (continued)
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 75 pin information (continued) table 21. or2c/2t04a and or2c/2t06a 144-pin tqfp pinout pin 2c/2t04a pad 2c/2t06a pad function pin 2c/2t04a pad 2c/2t06a pad function 1v dd v dd v dd 43 pb2b pb3b i/o 2v ss v ss v ss 44 pb2d pb3d i/o 3pl1c pl1a i/o-a0 45v dd v dd v dd 4 pl1b pl2d i/o 46 pb3a pb4a i/o 5 pl1a pl2a i/o-a1 47 pb3d pb4d i/o 6 pl2d pl3d i/o-a2 48 pb4a pb5a i/o 7 pl2a pl3a i/o-a3 49 pb4c pb5c i/o 8 pl3d pl4d i/o 50 pb4d pb5d i/o 9 pl3c pl4c i/o 51 pb5a pb6a i/o 10 pl3a pl4a i/o-a4 52 pb5c pb6c i/o 11 pl4d pl5d i/o-a5 53 pb5d pb6d i/o 12 pl4c pl5c i/o 54 v ss v ss v ss 13 pl4a pl5a i/o-a6 55 pb6a pb7a i/o 14 v ss v ss v ss 56 pb6c pb7c i/o 15 pl5d pl6d i/o 57 pb6d pb7d i/o 16 pl5c pl6c i/o 58 pb7a pb8a i/o-v dd 5 17 pl5a pl6a i/o-a7 59 pb7d pb8d i/o 18 v dd v dd v dd 60 pb8a pb9a i/o-hdc 19 pl6d pl7d i/o 61 pb8c pb9c i/o 20 pl6c pl7c i/o-v dd 5 62 pb8d pb9d i/o 21 pl6a pl7a i/o-a8 63 v dd v dd v dd 22 v ss v ss v ss 64 pb9a pb10a i/o- ldc 23 pl7d pl8d i/o-a9 65 pb9c pb10c i/o 24 pl7a pl8a i/o-a10 66 pb9d pb10d i/o 25 pl8d pl9d i/o 67 pb10a pb11a i/o- init 26 pl8c pl9c i/o 68 pb10c pb11d i/o 27 pl8a pl9a i/o-a11 69 pb10d pb12a i/o 28 pl9d pl10d i/o-a12 70 v ss v ss v ss 29 pl9c pl10c i/o 71 done done done 30 pl9a pl10a i/o-a13 72 v dd v dd v dd 31 pl10d pl11a i/o-a14 73 v ss v ss v ss 32 pl10c pl12d i/o 74 reset reset reset 33 pl10b pl12b i/o 75 prgm prgm prgm 34 pl10a pl12a i/o-a15 76 pr10a pr12a i/o-m0 35 v ss v ss v ss 77 pr10b pr12d i/o 36 cclk cclk cclk 78 pr10d pr11a i/o 37 v dd v dd v dd 79 pr9a pr10a i/o-m1 38 v ss v ss v ss 80 pr9c pr10c i/o 39 pb1a pb1a i/o-a16 81 pr9d pr10d i/o 40 pb1c pb1d i/o 82 pr8a pr9a i/o-m2 41 pb1d pb2a i/o-a17 83 pr8b pr9b i/o 42 pb2a pb3a i/o 84 pr8d pr9d i/o note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 76 lucent technologies inc. pin 2c/2t04a pad 2c/2t06a pad function pin 2c/2t04a pad 2c/2t06a pad function 85 pr7a pr8a i/o-m3 115 pt9c pt10d i/o 86 pr7d pr8d i/o 116 pt9b pt10c i/o 87 v ss v ss v ss 117 pt9a pt10a i/o-d6 88 pr6a pr7a i/o 118 v dd v dd v dd 89 pr6c pr7c i/o 119 pt8d pt9d i/o 90 pr6d pr7d i/o 120 pt8a pt9a i/o-d5 91 v dd v dd v dd 121 pt7d pt8d i/o 92 pr5a pr6a i/o 122 pt7b pt8b i/o 93 pr5c pr6c i/o 123 pt7a pt8a i/o-d4 94 pr5d pr6d i/o 124 pt6d pt7d i/o 95 v ss v ss v ss 125 pt6c pt7c i/o 96 pr4a pr5a i/o-v dd 5 126 pt6a pt7a i/o-d3 97 pr4c pr5c i/o 127 v ss v ss v ss 98 pr4d pr5d i/o 128 pt5d pt6d i/o 99 pr3a pr4a i/o-cs1 129 pt5c pt6c i/o 100 pr3d pr4d i/o 130 pt5a pt6a i/o-d2 101 pr2a pr3a i/o- cs0 131 pt4d pt5d i/o-d1 102 pr2d pr3d i/o 132 pt4c pt5c i/o 103 pr1a pr2a i/o- rd 133 pt4a pt5a i/o-d0/din 104 pr1b pr2c i/o 134 pt3d pt4d i/o 105 pr1c pr2d i/o 135 pt3a pt4a i/o-dout 106 pr1d pr1a i/o- wr 136 v dd v dd v dd 107 v ss v ss v ss 137 pt2d pt3d i/o-v dd 5 108 rd_cfg rd_cfg rd_cfg 138 pt2c pt3c i/o 109 v dd v dd v dd 139 pt2a pt3a i/o-tdi 110 v ss v ss v ss 140 pt1d pt2a i/o-tms 111 pt10d pt12d i/o 141 pt1c pt1d i/o 112 pt10c pt12a i/o-rdy/rclk 142 pt1a pt1a i/o-tck 113 pt10b pt11d i/o 143 v ss v ss v ss 114 pt9d pt11a i/o-d7 144 rd_data/ tdo rd_data/ tdo rd_data/tdo pin information (continued) table 21. or2c/2t04a and or2c/2t06a 144-pin tqfp pinout (continued) note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 77 pin information (continued) table 22. or2c/2t04a, or2c/2t06a, or2c/2t08a, and or2c/2t10a 160-pin qfp pinout pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad function 1v dd v dd v dd v dd v dd 2v ss v ss v ss v ss v ss 3 pl1d pl1d pl1d pl1d i/o 4 pl1c pl1a pl2d pl2d i/o-a0 5 pl1b pl2d pl3d pl3d i/o 6 pl1a pl2a pl3a pl3a i/o-a1 7 pl2d pl3d pl4d pl4a i/o-a2 8 pl2c pl3c pl4c pl5c i/o 9 pl2a pl3a pl4a pl5a i/o-a3 10 pl3d pl4d pl5d pl6d i/o 11 pl3c pl4c pl5c pl6c i/o 12 pl3a pl4a pl5a pl6a i/o-a4 13 pl4d pl5d pl6d pl7d i/o-a5 14 pl4c pl5c pl6c pl7c i/o 15 pl4a pl5a pl6a pl7a i/o-a6 16 v ss v ss v ss v ss v ss 17 pl5d pl6d pl7d pl8d i/o 18 pl5c pl6c pl7c pl8c i/o 19 pl5a pl6a pl7a pl8a i/o-a7 20 v dd v dd v dd v dd v dd 21 pl6d pl7d pl8d pl9d i/o 22 pl6c pl7c pl8c pl9c i/o-v dd 5 23 pl6a pl7a pl8a pl9a i/o-a8 24 v ss v ss v ss v ss v ss 25 pl7d pl8d pl9d pl10d i/o-a9 26 pl7b pl8b pl9b pl10b i/o 27 pl7a pl8a pl9a pl10a i/o-a10 28 pl8d pl9d pl10d pl11d i/o 29 pl8c pl9c pl10c pl11c i/o 30 pl8a pl9a pl10a pl11a i/o-a11 31 pl9d pl10d pl11d pl12d i/o-a12 32 pl9c pl10c pl11c pl12c i/o 33 pl9b pl10b pl11b pl12b i/o 34 pl9a pl10a pl11a pl13d i/o-a13 35 pl10d pl11a pl12a pl14c i/o-a14 36 pl10c pl12d pl13d pl15d i/o 37 pl10b pl12b pl14d pl16d i/o 38 pl10a pl12a pl14a pl16a i/o-a15 39 cclk cclk cclk cclk cclk 40 v ss v ss v ss v ss v ss note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 78 lucent technologies inc. 41 v dd v dd v dd v dd v dd 42 v ss v ss v ss v ss v ss 43 pb1a pb1a pb1a pb1a i/o-a16 44 pb1b pb1c pb2a pb2a i/o 45 pb1c pb1d pb2d pb2d i/o 46 pb1d pb2a pb3a pb3b i/o-a17 47 pb2a pb3a pb3d pb4d i/o 48 pb2b pb3b pb4a pb5a i/o 49 pb2c pb3c pb4c pb5c i/o 50 pb2d pb3d pb4d pb5d i/o 51 v dd v dd v dd v dd v dd 52 pb3a pb4a pb5a pb6a i/o 53 pb3d pb4d pb5d pb6d i/o 54 pb4a pb5a pb6a pb7a i/o 55 pb4c pb5c pb6c pb7c i/o 56 pb4d pb5d pb6d pb7d i/o 57 pb5a pb6a pb7a pb8a i/o 58 pb5c pb6c pb7c pb8c i/o 59 pb5d pb6d pb7d pb8d i/o 60 v ss v ss v ss v ss v ss 61 pb6a pb7a pb8a pb9a i/o 62 pb6c pb7c pb8c pb9c i/o 63 pb6d pb7d pb8d pb9d i/o 64 pb7a pb8a pb9a pb10a i/o-v dd 5 65 pb7d pb8d pb9d pb10d i/o 66 pb8a pb9a pb10a pb11a i/o-hdc 67 pb8c pb9c pb10c pb11c i/o 68 pb8d pb9d pb10d pb11d i/o 69 v dd v dd v dd v dd v dd 70 pb9a pb10a pb11a pb12a i/o- ldc 71 pb9b pb10b pb11d pb13a i/o 72 pb9c pb10c pb12a pb13b i/o 73 pb9d pb10d pb12b pb13c i/o 74 pb10a pb11a pb12c pb13d i/o- init 75 pb10b pb11c pb12d pb14a i/o 76 pb10c pb11d pb13d pb15d i/o 77 pb10d pb12a pb14d pb16d i/o 78 v ss v ss v ss v ss v ss 79 done done done done done 80 v dd v dd v dd v dd v dd 81 v ss v ss v ss v ss v ss pin information (continued) table 22. or2c/2t04a, or2c/2t06a, or2c/2t08a, and or2c/2t10a 160-pin qfp pinout (continued) pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad function note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 79 82 reset reset reset reset reset 83 prgm prgm prgm prgm prgm 84 pr10a pr12a pr14a pr16a i/o-m0 85 pr10b pr12d pr13a pr15a i/o 86 pr10c pr11a pr13d pr15d i/o 87 pr10d pr11b pr12a pr14a i/o 88 pr9a pr10a pr11a pr13b i/o-m1 89 pr9b pr10b pr11b pr13c i/o 90 pr9c pr10c pr11c pr12a i/o 91 pr9d pr10d pr11d pr12b i/o 92 pr8a pr9a pr10a pr11a i/o-m2 93 pr8b pr9b pr10b pr11b i/o 94 pr8d pr9d pr10d pr11d i/o 95 pr7a pr8a pr9a pr10a i/o-m3 96 pr7d pr8d pr9d pr10d i/o 97 v ss v ss v ss v ss v ss 98 pr6a pr7a pr8a pr9a i/o 99 pr6c pr7c pr8c pr9c i/o 100 pr6d pr7d pr8d pr9d i/o 101 v dd v dd v dd v dd v dd 102 pr5a pr6a pr7a pr8a i/o 103 pr5c pr6c pr7c pr8c i/o 104 pr5d pr6d pr7d pr8d i/o 105 v ss v ss v ss v ss v ss 106 pr4a pr5a pr6a pr7a i/o-v dd 5 107 pr4c pr5c pr6c pr7c i/o 108 pr4d pr5d pr6d pr7d i/o 109 pr3a pr4a pr5a pr6a i/o-cs1 110 pr3b pr4b pr5b pr6b i/o 111 pr3d pr4d pr5d pr6d i/o 112 pr2a pr3a pr4a pr5a i/o- cs0 113 pr2c pr3c pr4b pr4b i/o 114 pr2d pr3d pr4d pr4d i/o 115 pr1a pr2a pr3a pr3a i/o- rd 116 pr1b pr2c pr3c pr3c i/o 117 pr1c pr2d pr3d pr3d i/o 118 pr1d pr1a pr2a pr2a i/o- wr 119 v ss v ss v ss v ss v ss 120 rd_cfg rd_cfg rd_cfg rd_cfg rd_cfg 121 v dd v dd v dd v dd v dd 122 v ss v ss v ss v ss v ss pin information (continued) table 22. or2c/2t04a, or2c/2t06a, or2c/2t08a, and or2c/2t10a 160-pin qfp pinout (continued) pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad function note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 80 lucent technologies inc. 123 pt10d pt12d pt14d pt16d i/o 124 pt10c pt12a pt13d pt15d i/o-rdy/rclk 125 pt10b pt11d pt13a pt15a i/o 126 pt10a pt11c pt12d pt14d i/o 127 pt9d pt11a pt12c pt13d i/o-d7 128 pt9c pt10d pt12a pt13b i/o 129 pt9b pt10c pt11d pt13a i/o 130 pt9a pt10a pt11b pt12b i/o-d6 131 v dd v dd v dd v dd v dd 132 pt8d pt9d pt10d pt11d i/o 133 pt8a pt9a pt10a pt11a i/o-d5 134 pt7d pt8d pt9d pt10d i/o 135 pt7b pt8b pt9b pt10b i/o 136 pt7a pt8a pt9a pt10a i/o-d4 137 pt6d pt7d pt8d pt9d i/o 138 pt6c pt7c pt8c pt9c i/o 139 pt6a pt7a pt8a pt9a i/o-d3 140 v ss v ss v ss v ss v ss 141 pt5d pt6d pt7d pt8d i/o 142 pt5c pt6c pt7c pt8c i/o 143 pt5a pt6a pt7a pt8a i/o-d2 144 pt4d pt5d pt6d pt7d i/o-d1 145 pt4c pt5c pt6c pt7c i/o 146 pt4a pt5a pt6a pt7a i/o-d0/din 147 pt3d pt4d pt5d pt6d i/o 148 pt3c pt4c pt5c pt6c i/o 149 pt3a pt4a pt5a pt6a i/o-dout 150 v dd v dd v dd v dd v dd 151 pt2d pt3d pt4d pt5d i/o-v dd 5 152 pt2c pt3c pt4c pt5a i/o 153 pt2b pt3b pt4b pt4d i/o 154 pt2a pt3a pt4a pt4a i/o-tdi 155 pt1d pt2a pt3a pt3a i/o-tms 156 pt1c pt1d pt2a pt2a i/o 157 pt1b pt1c pt1d pt1d i/o 158 pt1a pt1a pt1a pt1a i/o-tck 159 v ss v ss v ss v ss v ss 160 rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo pin information (continued) table 22. or2c/2t04a, or2c/2t06a, or2c/2t08a, and or2c/2t10a 160-pin qfp pinout (continued) pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad function note: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 81 pin information (continued) table 23. or2c/2t04a, or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 208-pin sqfp/sqfp2 pinout pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function 1 vss vss vss vss vss vss vss vss vss 2 vss vss vss vss vss vss vss vss vss 3 pl1d pl1d pl1d pl1d pl1d pl1d pl1d pl1d i/o 4 pl1c pl1a pl2d pl2d pl2d pl2d pl2d pl3d i/o-a0 5 pl1b pl2d pl3d pl3d pl3d pl4d pl4d pl5d i/o-vdd5 6 see note pl2c pl3c pl3c pl3a pl4a pl4a pl6d i/o 7 pl1a pl2a pl3a pl3a pl4a pl5a pl5a pl8d i/o-a1 8 pl2d pl3d pl4d pl4a pl5a pl6a pl6a pl9a i/o-a2 9 pl2c pl3c pl4c pl5c pl6d pl7d pl7d pl10d i/o 10 pl2b pl3b pl4b pl5b pl6b pl7b pl7b pl10b i/o 11 pl2a pl3a pl4a pl5a pl6a pl7a pl7a pl10a i/o-a3 12 vdd vdd vdd vdd vdd vdd vdd vdd vdd 13 pl3d pl4d pl5d pl6d pl7d pl8d pl8d pl11d i/o 14 pl3c pl4c pl5c pl6c pl7c pl8c pl8a pl11a i/o 15 pl3b pl4b pl5b pl6b pl7b pl8b pl9d pl12d i/o 16 pl3a pl4a pl5a pl6a pl7a pl8a pl9a pl12a i/o-a4 17 pl4d pl5d pl6d pl7d pl8d pl9d pl10d pl13d i/o-a5 18 pl4c pl5c pl6c pl7c pl8c pl9c pl10a pl13a i/o 19 pl4b pl5b pl6b pl7b pl8b pl9b pl11d pl14d i/o 20 pl4a pl5a pl6a pl7a pl8a pl9a pl11a pl14a i/o-a6 21 vss vss vss vss vss vss vss vss vss 22 pl5d pl6d pl7d pl8d pl9d pl10d pl12d pl15d i/o 23 pl5c pl6c pl7c pl8c pl9c pl10c pl12c pl15c i/o 24 pl5b pl6b pl7b pl8b pl9b pl10b pl12b pl15b i/o 25 pl5a pl6a pl7a pl8a pl9a pl10a pl12a pl15a i/o-a7 26 vdd vdd vdd vdd vdd vdd vdd vdd vdd 27 pl6d pl7d pl8d pl9d pl10d pl11d pl13d pl16d i/o 28 pl6c pl7c pl8c pl9c pl10c pl11c pl13c pl16c i/o-vdd5 29 pl6b pl7b pl8b pl9b pl10b pl11b pl13b pl16b i/o 30 pl6a pl7a pl8a pl9a pl10a pl11a pl13a pl16a i/o-a8 31 vss vss vss vss vss vss vss vss vss 32 pl7d pl8d pl9d pl10d pl11d pl12d pl14d pl17d i/o-a9 33 pl7c pl8c pl9c pl10c pl11c pl12c pl14a pl17a i/o 34 pl7b pl8b pl9b pl10b pl11b pl12b pl15d pl18d i/o 35 pl7a pl8a pl9a pl10a pl11a pl12a pl15a pl18a i/o-a10 36 pl8d pl9d pl10d pl11d pl12d pl13d pl16d pl19d i/o 37 pl8c pl9c pl10c pl11c pl12c pl13c pl16a pl19a i/o 38 pl8b pl9b pl10b pl11b pl12b pl13b pl17d pl20d i/o 39 pl8a pl9a pl10a pl11a pl12a pl13a pl17a pl20a i/o-a11 40 vdd vdd vdd vdd vdd vdd vdd vdd vdd 41 pl9d pl10d pl11d pl12d pl13d pl14d pl18d pl21d i/o-a12 42 pl9c pl10c pl11c pl12c pl13b pl14b pl18b pl21b i/o 43 pl9b pl10b pl11b pl12b pl14d pl15d pl19d pl22d i/o notes: the or2c04a and or2t04a do not have bond pads connected to 208-pin sqfp package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 1 66, 201, and 203. the pins labeled i/o-vdd5 are user i/os for the or2cxxa and or2txxb series, but they are connected to vdd5 for the or2txxa seri es.
data sheet orca series 2 fpgas june 1999 82 lucent technologies inc. 44 pl9a pl10a pl11a pl13d pl14b pl15b pl19b pl22b i/o-a13 45 see note pl11d pl12d pl13b pl15d pl16d pl20d pl23d i/o 46 pl10d pl11a pl12a pl14c pl16d pl17d pl21d pl25a i/o-a14 47 see note pl12d pl13d pl15d pl17d pl18d pl22d pl27d i/o 48 pl10c pl12c pl13a pl15a pl17a pl19d pl23d pl28d i/o 49 pl10b pl12b pl14d pl16d pl18c pl19a pl23a pl28a i/o 50 pl10a pl12a pl14a pl16a pl18a pl20a pl24a pl30a i/o-a15 51 vss vss vss vss vss vss vss vss vss 52 cclk cclk cclk cclk cclk cclk cclk cclk cclk 53 vss vss vss vss vss vss vss vss vss 54 vss vss vss vss vss vss vss vss vss 55 pb1a pb1a pb1a pb1a pb1a pb1a pb1a pb1a i/o-a16 56 see note pb1b pb1d pb1d pb1d pb2a pb2a pb3a i/o 57 pb1b pb1c pb2a pb2a pb2a pb2d pb2d pb3d i/o-vdd5 58 pb1c pb1d pb2d pb2d pb2d pb3d pb3d pb4d i/o 59 pb1d pb2a pb3a pb3b pb3d pb4d pb4d pb5d i/o-a17 60 see note pb2d pb3d pb4d pb4d pb5d pb5d pb6d i/o 61 pb2a pb3a pb4a pb5a pb5b pb6b pb6b pb7d i/o 62 pb2b pb3b pb4b pb5b pb5d pb6d pb6d pb8d i/o 63 pb2c pb3c pb4c pb5c pb6b pb7b pb7b pb9d i/o 64 pb2d pb3d pb4d pb5d pb6d pb7d pb7d pb10d i/o 65 vdd vdd vdd vdd vdd vdd vdd vdd vdd 66 pb3a pb4a pb5a pb6a pb7a pb8a pb8a pb11a i/o 67 pb3b pb4b pb5b pb6b pb7b pb8b pb8d pb11d i/o 68 pb3c pb4c pb5c pb6c pb7c pb8c pb9a pb12a i/o 69 pb3d pb4d pb5d pb6d pb7d pb8d pb9d pb12d i/o 70 pb4a pb5a pb6a pb7a pb8a pb9a pb10a pb13a i/o 71 pb4b pb5b pb6b pb7b pb8b pb9b pb10d pb13d i/o 72 pb4c pb5c pb6c pb7c pb8c pb9c pb11a pb14a i/o 73 pb4d pb5d pb6d pb7d pb8d pb9d pb11d pb14d i/o 74 vss vss vss vss vss vss vss vss vss 75 pb5a pb6a pb7a pb8a pb9a pb10a pb12a pb15a i/o 76 pb5b pb6b pb7b pb8b pb9b pb10b pb12b pb15b i/o 77 pb5c pb6c pb7c pb8c pb9c pb10c pb12c pb15c i/o 78 pb5d pb6d pb7d pb8d pb9d pb10d pb12d pb15d i/o 79 vss vss vss vss vss vss vss vss vss 80 pb6a pb7a pb8a pb9a pb10a pb11a pb13a pb16a i/o 81 pb6b pb7b pb8b pb9b pb10b pb11b pb13b pb16b i/o 82 pb6c pb7c pb8c pb9c pb10c pb11c pb13c pb16c i/o 83 pb6d pb7d pb8d pb9d pb10d pb11d pb13d pb16d i/o 84 vss vss vss vss vss vss vss vss vss 85 pb7a pb8a pb9a pb10a pb11a pb12a pb14a pb17a i/o-vdd5 86 pb7b pb8b pb9b pb10b pb11b pb12b pb14d pb17d i/o pin information (continued) table 23. or2c/2t04a, or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 208-pin sqfp/sqfp2 pinout (continued) pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2c04a and or2t04a do not have bond pads connected to 208-pin sqfp package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 1 66, 201, and 203. the pins labeled i/o-vdd5 are user i/os for the or2cxxa and or2txxb series, but they are connected to vdd5 for the or2txxa seri es.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 83 87 pb7c pb8c pb9c pb10c pb11c pb12c pb15a pb18a i/o 88 pb7d pb8d pb9d pb10d pb11d pb12d pb15d pb18d i/o 89 pb8a pb9a pb10a pb11a pb12a pb13a pb16a pb19a i/o-hdc 90 pb8b pb9b pb10b pb11b pb12b pb13b pb16d pb19d i/o 91 pb8c pb9c pb10c pb11c pb12c pb13c pb17a pb20a i/o 92 pb8d pb9d pb10d pb11d pb12d pb13d pb17d pb20d i/o 93 vdd vdd vdd vdd vdd vdd vdd vdd vdd 94 pb9a pb10a pb11a pb12a pb13a pb14a pb18a pb21a i/o-ldc 95 pb9b pb10b pb11d pb13a pb13d pb14d pb18d pb22d i/o 96 pb9c pb10c pb12a pb13b pb14a pb15a pb19a pb23a i/o 97 pb9d pb10d pb12b pb13c pb14d pb15d pb19d pb24d i/o 98 pb10a pb11a pb12c pb13d pb15a pb16a pb20a pb25a i/o-init 99 pb10b pb11c pb12d pb14a pb16a pb17a pb21a pb26a i/o 100 pb10c pb11d pb13a pb15a pb17a pb18a pb22a pb27a i/o 101 pb10d pb12a pb13d pb15d pb18a pb19d pb23d pb28d i/o 102 see note pb12d pb14d pb16d pb18d pb20d pb24d pb30d i/o 103 vss vss vss vss vss vss vss vss vss 104 done done done done done done done done done 105 vss vss vss vss vss vss vss vss vss 106 reset reset reset reset reset reset reset reset reset 107 prgm prgm prgm prgm prgm prgm prgm prgm prgm 108 pr10a pr12a pr14a pr16a pr18a pr20a pr24a pr30a i/o-m0 109 pr10b pr12d pr13a pr15a pr18d pr19a pr23a pr28a i/o 110 pr10c pr11a pr13d pr15d pr17b pr18a pr22a pr27a i/o 111 pr10d pr11b pr12a pr14a pr16a pr17a pr21a pr26a i/o 112 pr9a pr10a pr11a pr13b pr15d pr16d pr20d pr23d i/o-m1 113 pr9b pr10b pr11b pr13c pr14a pr15a pr19a pr22a i/o 114 pr9c pr10c pr11c pr12a pr14d pr15d pr19d pr22d i/o-vdd5 115 pr9d pr10d pr11d pr12b pr13a pr14a pr18a pr21a i/o 116 vdd vdd vdd vdd vdd vdd vdd vdd vdd 117 pr8a pr9a pr10a pr11a pr12a pr13a pr17a pr20a i/o-m2 118 pr8b pr9b pr10b pr11b pr12b pr13b pr17d pr20d i/o 119 pr8c pr9c pr10c pr11c pr12c pr13c pr16a pr19a i/o 120 pr8d pr9d pr10d pr11d pr12d pr13d pr16d pr19d i/o 121 pr7a pr8a pr9a pr10a pr11a pr12a pr15a pr18a i/o-m3 122 pr7b pr8b pr9b pr10b pr11b pr12b pr15d pr18d i/o 123 pr7c pr8c pr9c pr10c pr11c pr12c pr14a pr17a i/o 124 pr7d pr8d pr9d pr10d pr11d pr12d pr14d pr17d i/o 125 vss vss vss vss vss vss vss vss vss 126 pr6a pr7a pr8a pr9a pr10a pr11a pr13a pr16a i/o 127 pr6b pr7b pr8b pr9b pr10b pr11b pr13b pr16b i/o 128 pr6c pr7c pr8c pr9c pr10c pr11c pr13c pr16c i/o 129 pr6d pr7d pr8d pr9d pr10d pr11d pr13d pr16d i/o pin information (continued) table 23. or2c/2t04a, or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 208-pin sqfp/sqfp2 pinout (continued) pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2c04a and or2t04a do not have bond pads connected to 208-pin sqfp package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 1 66, 201, and 203. the pins labeled i/o-vdd5 are user i/os for the or2cxxa and or2txxb series, but they are connected to vdd5 for the or2txxa seri es.
data sheet orca series 2 fpgas june 1999 84 lucent technologies inc. 130 vdd vdd vdd vdd vdd vdd vdd vdd vdd 131 pr5a pr6a pr7a pr8a pr9a pr10a pr12a pr15a i/o 132 pr5b pr6b pr7b pr8b pr9b pr10b pr12b pr15b i/o 133 pr5c pr6c pr7c pr8c pr9c pr10c pr12c pr15c i/o 134 pr5d pr6d pr7d pr8d pr9d pr10d pr12d pr15d i/o 135 vss vss vss vss vss vss vss vss vss 136 pr4a pr5a pr6a pr7a pr8a pr9a pr11a pr14a i/o-vdd5 137 pr4b pr5b pr6b pr7b pr8b pr9b pr11d pr14d i/o 138 pr4c pr5c pr6c pr7c pr8c pr9c pr10a pr13a i/o 139 pr4d pr5d pr6d pr7d pr8d pr9d pr10d pr13d i/o 140 pr3a pr4a pr5a pr6a pr7a pr8a pr9a pr12a i/o-cs1 141 pr3b pr4b pr5b pr6b pr7b pr8b pr9d pr12d i/o 142 pr3c pr4c pr5c pr6c pr7c pr8c pr8a pr11a i/o 143 pr3d pr4d pr5d pr6d pr7d pr8d pr8d pr11d i/o 144 vdd vdd vdd vdd vdd vdd vdd vdd vdd 145 pr2a pr3a pr4a pr5a pr6a pr7a pr7a pr10a i/o-cs0 146 pr2b pr3b pr4b pr4b pr6b pr7b pr7b pr10b i/o 147 pr2c pr3c pr4c pr4c pr5b pr6b pr6b pr9b i/o 148 pr2d pr3d pr4d pr4d pr5d pr6d pr6d pr9d i/o 149 pr1a pr2a pr3a pr3a pr4a pr5a pr5a pr8a i/o-rd 150 pr1b pr2c pr3c pr3c pr4d pr5d pr5d pr6a i/o 151 pr1c pr2d pr3d pr3d pr3a pr4a pr4a pr5a i/o 152 pr1d pr1a pr2a pr2a pr2a pr3a pr3a pr4a i/o-wr 153 see note pr1c pr2d pr2d pr2c pr2a pr2a pr3a i/o 154 see note pr1d pr1a pr1a pr1a pr1a pr1a pr2a i/o 155 vss vss vss vss vss vss vss vss vss 156 rd_cfg rd_cfg rd_cfg rd_cfg rd_cfg rd_cfg rd_cfg rd_cfg rd_cfg 157 vss vss vss vss vss vss vss vss vss 158 vss vss vss vss vss vss vss vss vss 159 pt10d pt12d pt14d pt16d pt18d pt20d pt24d pt30d i/o 160 pt10c pt12a pt13d pt15d pt17d pt19a pt23a pt28a i/o-rdy/rclk 161 pt10b pt11d pt13a pt15a pt16d pt17d pt21d pt26d i/o 162 pt10a pt11c pt12d pt14d pt16a pt17a pt21a pt26a i/o 163 pt9d pt11a pt12c pt13d pt15d pt16d pt20d pt25d i/o-d7 164 pt9c pt10d pt12a pt13b pt14d pt15d pt19d pt24d i/o-vdd5 165 pt9b pt10c pt11d pt13a pt14a pt15a pt19a pt23d i/o 166 see note pt10b pt11c pt12d pt13d pt14d pt18d pt22d i/o 167 pt9a pt10a pt11b pt12b pt13b pt14b pt18b pt21d i/o-d6 168 vdd vdd vdd vdd vdd vdd vdd vdd vdd 169 pt8d pt9d pt10d pt11d pt12d pt13d pt17d pt20d i/o 170 pt8c pt9c pt10c pt11c pt12c pt13c pt17a pt20a i/o 171 pt8b pt9b pt10b pt11b pt12b pt13b pt16d pt19d i/o 172 pt8a pt9a pt10a pt11a pt12a pt13a pt16a pt19a i/o-d5 pin information (continued) table 23. or2c/2t04a, or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 208-pin sqfp/sqfp2 pinout (continued) pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2c04a and or2t04a do not have bond pads connected to 208-pin sqfp package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 1 66, 201, and 203. the pins labeled i/o-vdd5 are user i/os for the or2cxxa and or2txxb series, but they are connected to vdd5 for the or2txxa seri es.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 85 173 pt7d pt8d pt9d pt10d pt11d pt12d pt15d pt18d i/o 174 pt7c pt8c pt9c pt10c pt11c pt12c pt15a pt18a i/o 175 pt7b pt8b pt9b pt10b pt11b pt12b pt14d pt17d i/o 176 pt7a pt8a pt9a pt10a pt11a pt12a pt14a pt17a i/o-d4 177 vss vss vss vss vss vss vss vss vss 178 pt6d pt7d pt8d pt9d pt10d pt11d pt13d pt16d i/o 179 pt6c pt7c pt8c pt9c pt10c pt11c pt13c pt16c i/o 180 pt6b pt7b pt8b pt9b pt10b pt11b pt13b pt16b i/o 181 pt6a pt7a pt8a pt9a pt10a pt11a pt13a pt16a i/o-d3 182 vss vss vss vss vss vss vss vss vss 183 pt5d pt6d pt7d pt8d pt9d pt10d pt12d pt15d i/o 184 pt5c pt6c pt7c pt8c pt9c pt10c pt12c pt15c i/o 185 pt5b pt6b pt7b pt8b pt9b pt10b pt12b pt15b i/o-vdd5 186 pt5a pt6a pt7a pt8a pt9a pt10a pt12a pt15a i/o-d2 187 vss vss vss vss vss vss vss vss vss 188 pt4d pt5d pt6d pt7d pt8d pt9d pt11d pt14d i/o-d1 189 pt4c pt5c pt6c pt7c pt8c pt9c pt11a pt14a i/o 190 pt4b pt5b pt6b pt7b pt8b pt9b pt10d pt13d i/o 191 pt4a pt5a pt6a pt7a pt8a pt9a pt10a pt13a i/o-d0/din 192 pt3d pt4d pt5d pt6d pt7d pt8d pt9d pt12d i/o 193 pt3c pt4c pt5c pt6c pt7c pt8c pt9a pt12a i/o 194 pt3b pt4b pt5b pt6b pt7b pt8b pt8d pt11d i/o 195 pt3a pt4a pt5a pt6a pt7a pt8a pt8a pt11a i/o-dout 196 vdd vdd vdd vdd vdd vdd vdd vdd vdd 197 pt2d pt3d pt4d pt5d pt6d pt7d pt7d pt10d i/o 198 pt2c pt3c pt4c pt5a pt6a pt7a pt7a pt9a i/o 199 pt2b pt3b pt4b pt4d pt5c pt6c pt6c pt8a i/o 200 pt2a pt3a pt4a pt4a pt5a pt6a pt6a pt7a i/o-tdi 201 see note pt2d pt3d pt3d pt4a pt5a pt5a pt6a i/o 202 pt1d pt2a pt3a pt3a pt3a pt4a pt4a pt5a i/o-tms 203 see note pt1d pt2d pt2d pt2c pt3a pt3a pt4a i/o 204 pt1c pt1c pt2a pt2a pt2a pt2a pt2a pt3a i/o 205 pt1b pt1b pt1d pt1d pt1d pt1d pt1d pt2d i/o 206 pt1a pt1a pt1a pt1a pt1a pt1a pt1a pt1a i/o-tck 207 vss vss vss vss vss vss vss vss vss 208 rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/tdo pin information (continued) table 23. or2c/2t04a, or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 208-pin sqfp/sqfp2 pinout (continued) pin 2c/2t04a pad 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2c04a and or2t04a do not have bond pads connected to 208-pin sqfp package pin numbers 6, 45, 47, 56, 60, 102, 153, 154, 1 66, 201, and 203. the pins labeled i/o-vdd5 are user i/os for the or2cxxa and or2txxb series, but they are connected to vdd5 for the or2txxa seri es.
data sheet orca series 2 fpgas june 1999 86 lucent technologies inc. pin information (continued) table 24. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 240-pin sqfp/sqfp2 pinout pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function 1v ss v ss v ss v ss v ss v ss v ss v ss 2v dd v dd v dd v dd v dd v dd v dd v dd 3 pl1d pl1d pl1d pl1d pl1d pl1d pl1d i/o 4 pl1c pl1b pl1b pl1c pl1c pl1c pl1a i/o 5 pl1b pl1a pl1a pl1b pl1b pl1b pl2d i/o 6 pl1a pl2d pl2d pl2d pl2d pl2d pl3d i/o-a0 7v ss v ss v ss v ss v ss v ss v ss v ss 8 pl2d pl3d pl3d pl3d pl4d pl4d pl5d i/o-v dd 5 9 pl2c pl3c pl3c pl3a pl4a pl4a pl6d i/o 10 pl2b pl3b pl3b pl4d pl5d pl5d pl7d i/o 11 pl2a pl3a pl3a pl4a pl5a pl5a pl8d i/o-a1 12 pl3d pl4d pl4a pl5a pl6a pl6a pl9a i/o-a2 13 pl3c pl4c pl5c pl6d pl7d pl7d pl10d i/o 14 pl3b pl4b pl5b pl6b pl7b pl7b pl10b i/o 15 pl3a pl4a pl5a pl6a pl7a pl7a pl10a i/o-a3 16 v dd v dd v dd v dd v dd v dd v dd v dd 17 pl4d pl5d pl6d pl7d pl8d pl8d pl11d i/o 18 pl4c pl5c pl6c pl7c pl8c pl8a pl11a i/o 19 pl4b pl5b pl6b pl7b pl8b pl9d pl12d i/o 20 pl4a pl5a pl6a pl7a pl8a pl9a pl12a i/o-a4 21 pl5d pl6d pl7d pl8d pl9d pl10d pl13d i/o-a5 22 pl5c pl6c pl7c pl8c pl9c pl10a pl13a i/o 23 pl5b pl6b pl7b pl8b pl9b pl11d pl14d i/o 24 pl5a pl6a pl7a pl8a pl9a pl11a pl14a i/o-a6 25 v ss v ss v ss v ss v ss v ss v ss v ss 26 pl6d pl7d pl8d pl9d pl10d pl12d pl15d i/o 27 pl6c pl7c pl8c pl9c pl10c pl12c pl15c i/o 28 pl6b pl7b pl8b pl9b pl10b pl12b pl15b i/o 29 pl6a pl7a pl8a pl9a pl10a pl12a pl15a i/o-a7 30 v dd v dd v dd v dd v dd v dd v dd v dd 31 pl7d pl8d pl9d pl10d pl11d pl13d pl16d i/o 32 pl7c pl8c pl9c pl10c pl11c pl13c pl16c i/o-v dd 5 33 pl7b pl8b pl9b pl10b pl11b pl13b pl16b i/o 34 pl7a pl8a pl9a pl10a pl11a pl13a pl16a i/o-a8 35 v ss v ss v ss v ss v ss v ss v ss v ss 36 pl8d pl9d pl10d pl11d pl12d pl14d pl17d i/o-a9 37 pl8c pl9c pl10c pl11c pl12c pl14a pl17a i/o 38 pl8b pl9b pl10b pl11b pl12b pl15d pl18d i/o 39 pl8a pl9a pl10a pl11a pl12a pl15a pl18a i/o-a10 40 pl9d pl10d pl11d pl12d pl13d pl16d pl19d i/o 41 pl9c pl10c pl11c pl12c pl13c pl16a pl19a i/o 42 pl9b pl10b pl11b pl12b pl13b pl17d pl20d i/o notes: the or2c/2t08a and or2c/2t10a do not have bond pads connected to 240-pin sqfp package pin numbers 113 and 188. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 87 43 pl9a pl10a pl11a pl12a pl13a pl17a pl20a i/o-a11 44 v dd v dd v dd v dd v dd v dd v dd v dd 45 pl10d pl11d pl12d pl13d pl14d pl18d pl21d i/o-a12 46 pl10c pl11c pl12c pl13b pl14b pl18b pl21b i/o 47 pl10b pl11b pl12b pl14d pl15d pl19d pl22d i/o 48 pl10a pl11a pl13d pl14b pl15b pl19b pl22b i/o-a13 49 pl11d pl12d pl13b pl14a pl15a pl19a pl22a i/o 50 pl11c pl12c pl13a pl15d pl16d pl20d pl23d i/o 51 pl11b pl12b pl14d pl15b pl16b pl20b pl24d i/o 52 pl11a pl12a pl14c pl16d pl17d pl21d pl25a i/o-a14 53 v ss v ss v ss v ss v ss v ss v ss v ss 54 pl12d pl13d pl15d pl17d pl18d pl22d pl27d i/o 55 pl12c pl13a pl15a pl17a pl19d pl23d pl28d i/o 56 pl12b pl14d pl16d pl18c pl19a pl23a pl28a i/o 57 pl12a pl14a pl16a pl18a pl20a pl24a pl30a i/o-a15 58 v ss v ss v ss v ss v ss v ss v ss v ss 59 cclk cclk cclk cclk cclk cclk cclk cclk 60 v dd v dd v dd v dd v dd v dd v dd v dd 61 v ss v ss v ss v ss v ss v ss v ss v ss 62 v ss v ss v ss v ss v ss v ss v ss v ss 63 pb1a pb1a pb1a pb1a pb1a pb1a pb1a i/o-a16 64 pb1b pb1d pb1d pb1d pb2a pb2a pb3a i/o 65 pb1c pb2a pb2a pb2a pb2d pb2d pb3d i/o-v dd 5 66 pb1d pb2d pb2d pb2d pb3d pb3d pb4d i/o 67 v ss v ss v ss v ss v ss v ss v ss v ss 68 pb2a pb3a pb3b pb3d pb4d pb4d pb5d i/o-a17 69 pb2b pb3b pb4b pb4d pb5d pb5d pb6d i/o 70 pb2c pb3c pb4c pb5a pb6a pb6a pb7a i/o 71 pb2d pb3d pb4d pb5b pb6b pb6b pb7d i/o 72 pb3a pb4a pb5a pb5d pb6d pb6d pb8d i/o 73 pb3b pb4b pb5b pb6a pb7a pb7a pb9a i/o 74 pb3c pb4c pb5c pb6b pb7b pb7b pb9d i/o 75 pb3d pb4d pb5d pb6d pb7d pb7d pb10d i/o 76 v dd v dd v dd v dd v dd v dd v dd v dd 77 pb4a pb5a pb6a pb7a pb8a pb8a pb11a i/o 78 pb4b pb5b pb6b pb7b pb8b pb8d pb11d i/o 79 pb4c pb5c pb6c pb7c pb8c pb9a pb12a i/o 80 pb4d pb5d pb6d pb7d pb8d pb9d pb12d i/o 81 pb5a pb6a pb7a pb8a pb9a pb10a pb13a i/o 82 pb5b pb6b pb7b pb8b pb9b pb10d pb13d i/o 83 pb5c pb6c pb7c pb8c pb9c pb11a pb14a i/o 84 pb5d pb6d pb7d pb8d pb9d pb11d pb14d i/o pin information (continued) table 24. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 240-pin sqfp/sqfp2 pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2c/2t08a and or2c/2t10a do not have bond pads connected to 240-pin sqfp package pin numbers 113 and 188. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 88 lucent technologies inc. 85 v ss v ss v ss v ss v ss v ss v ss v ss 86 pb6a pb7a pb8a pb9a pb10a pb12a pb15a i/o 87 pb6b pb7b pb8b pb9b pb10b pb12b pb15b i/o 88 pb6c pb7c pb8c pb9c pb10c pb12c pb15c i/o 89 pb6d pb7d pb8d pb9d pb10d pb12d pb15d i/o 90 v ss v ss v ss v ss v ss v ss v ss v ss 91 pb7a pb8a pb9a pb10a pb11a pb13a pb16a i/o 92 pb7b pb8b pb9b pb10b pb11b pb13b pb16b i/o 93 pb7c pb8c pb9c pb10c pb11c pb13c pb16c i/o 94 pb7d pb8d pb9d pb10d pb11d pb13d pb16d i/o 95 v ss v ss v ss v ss v ss v ss v ss v ss 96 pb8a pb9a pb10a pb11a pb12a pb14a pb17a i/o-v dd 5 97 pb8b pb9b pb10b pb11b pb12b pb14d pb17d i/o 98 pb8c pb9c pb10c pb11c pb12c pb15a pb18a i/o 99 pb8d pb9d pb10d pb11d pb12d pb15d pb18d i/o 100 pb9a pb10a pb11a pb12a pb13a pb16a pb19a i/o-hdc 101 pb9b pb10b pb11b pb12b pb13b pb16d pb19d i/o 102 pb9c pb10c pb11c pb12c pb13c pb17a pb20a i/o 103 pb9d pb10d pb11d pb12d pb13d pb17d pb20d i/o 104 v dd v dd v dd v dd v dd v dd v dd v dd 105 pb10a pb11a pb12a pb13a pb14a pb18a pb21a i/o-ldc 106 pb10b pb11d pb13a pb13d pb14d pb18d pb22d i/o 107 pb10c pb12a pb13b pb14a pb15a pb19a pb23a i/o 108 pb10d pb12b pb13c pb14d pb15d pb19d pb24d i/o 109 pb11a pb12c pb13d pb15a pb16a pb20a pb25a i/o-init 110 pb11b pb12d pb14a pb15d pb16d pb20d pb25d i/o 111 pb11c pb13a pb15a pb16a pb17a pb21a pb26a i/o 112 pb11d pb13b pb15b pb16d pb17d pb21d pb26d i/o 113 v ss see note see note v ss v ss v ss v ss v ss 114 pb12a pb13d pb15d pb17a pb18a pb22a pb27a i/o 115 pb12b pb14a pb16a pb17d pb19a pb23a pb28a i/o 116 pb12c pb14b pb16b pb18a pb19d pb23d pb28d i/o 117 pb12d pb14d pb16d pb18d pb20d pb24d pb30d i/o 118 v ss v ss v ss v ss v ss v ss v ss v ss 119 done done done done done done done done 120 v dd v dd v dd v dd v dd v dd v dd v dd 121 v ss v ss v ss v ss v ss v ss v ss v ss 122 reset reset reset reset reset reset reset reset 123 prgm prgm prgm prgm prgm prgm prgm prgm 124 pr12a pr14a pr16a pr18a pr20a pr24a pr30a i/o-m0 125 pr12b pr14d pr16d pr18c pr20d pr24d pr29d i/o 126 pr12c pr13a pr15a pr18d pr19a pr23a pr28a i/o pin information (continued) table 24. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 240-pin sqfp/sqfp2 pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2c/2t08a and or2c/2t10a do not have bond pads connected to 240-pin sqfp package pin numbers 113 and 188. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 89 127 pr12d pr13d pr15d pr17b pr18a pr22a pr27a i/o 128 v ss v ss v ss v ss v ss v ss v ss v ss 129 pr11a pr12a pr14a pr16a pr17a pr21a pr26a i/o 130 pr11b pr12b pr14c pr16d pr17d pr21d pr25a i/o 131 pr11c pr12c pr14d pr15a pr16a pr20a pr24a i/o 132 pr11d pr12d pr13a pr15c pr16c pr20c pr24d i/o 133 pr10a pr11a pr13b pr15d pr16d pr20d pr23d i/o-m1 134 pr10b pr11b pr13c pr14a pr15a pr19a pr22a i/o 135 pr10c pr11c pr12a pr14d pr15d pr19d pr22d i/o-v dd 5 136 pr10d pr11d pr12b pr13a pr14a pr18a pr21a i/o 137 v dd v dd v dd v dd v dd v dd v dd v dd 138 pr9a pr10a pr11a pr12a pr13a pr17a pr20a i/o-m2 139 pr9b pr10b pr11b pr12b pr13b pr17d pr20d i/o 140 pr9c pr10c pr11c pr12c pr13c pr16a pr19a i/o 141 pr9d pr10d pr11d pr12d pr13d pr16d pr19d i/o 142 pr8a pr9a pr10a pr11a pr12a pr15a pr18a i/o-m3 143 pr8b pr9b pr10b pr11b pr12b pr15d pr18d i/o 144 pr8c pr9c pr10c pr11c pr12c pr14a pr17a i/o 145 pr8d pr9d pr10d pr11d pr12d pr14d pr17d i/o 146 v ss v ss v ss v ss v ss v ss v ss v ss 147 pr7a pr8a pr9a pr10a pr11a pr13a pr16a i/o 148 pr7b pr8b pr9b pr10b pr11b pr13b pr16b i/o 149 pr7c pr8c pr9c pr10c pr11c pr13c pr16c i/o 150 pr7d pr8d pr9d pr10d pr11d pr13d pr16d i/o 151 v dd v dd v dd v dd v dd v dd v dd v dd 152 pr6a pr7a pr8a pr9a pr10a pr12a pr15a i/o 153 pr6b pr7b pr8b pr9b pr10b pr12b pr15b i/o 154 pr6c pr7c pr8c pr9c pr10c pr12c pr15c i/o 155 pr6d pr7d pr8d pr9d pr10d pr12d pr15d i/o 156 v ss v ss v ss v ss v ss v ss v ss v ss 157 pr5a pr6a pr7a pr8a pr9a pr11a pr14a i/o-v dd 5 158 pr5b pr6b pr7b pr8b pr9b pr11d pr14d i/o 159 pr5c pr6c pr7c pr8c pr9c pr10a pr13a i/o 160 pr5d pr6d pr7d pr8d pr9d pr10d pr13d i/o 161 pr4a pr5a pr6a pr7a pr8a pr9a pr12a i/o-cs1 162 pr4b pr5b pr6b pr7b pr8b pr9d pr12d i/o 163 pr4c pr5c pr6c pr7c pr8c pr8a pr11a i/o 164 pr4d pr5d pr6d pr7d pr8d pr8d pr11d i/o 165 v dd v dd v dd v dd v dd v dd v dd v dd 166 pr3a pr4a pr5a pr6a pr7a pr7a pr10a i/o-cs0 167 pr3b pr4b pr4b pr6b pr7b pr7b pr10b i/o 168 pr3c pr4c pr4c pr5b pr6b pr6b pr9b i/o pin information (continued) table 24. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 240-pin sqfp/sqfp2 pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2c/2t08a and or2c/2t10a do not have bond pads connected to 240-pin sqfp package pin numbers 113 and 188. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 90 lucent technologies inc. 169 pr3d pr4d pr4d pr5d pr6d pr6d pr9d i/o 170 pr2a pr3a pr3a pr4a pr5a pr5a pr8a i/o-rd 171 pr2b pr3b pr3b pr4b pr5b pr5b pr7a i/o 172 pr2c pr3c pr3c pr4d pr5d pr5d pr6a i/o 173 pr2d pr3d pr3d pr3a pr4a pr4a pr5a i/o 174 v ss v ss v ss v ss v ss v ss v ss v ss 175 pr1a pr2a pr2a pr2a pr3a pr3a pr4a i/o-wr 176 pr1b pr2d pr2d pr2c pr2a pr2a pr3a i/o 177 pr1c pr1a pr1a pr1a pr1a pr1a pr2a i/o 178 pr1d pr1d pr1d pr1d pr1d pr1d pr1d i/o 179 v ss v ss v ss v ss v ss v ss v ss v ss 180 rd_cfgn rd_cfgn rd_cfgn rd_cfgn rd_cfgn rd_cfgn rd_cfgn rd_cfgn 181 v ss v ss v ss v ss v ss v ss v ss v ss 182 v dd v dd v dd v dd v dd v dd v dd v dd 183 v ss v ss v ss v ss v ss v ss v ss v ss 184 pt12d pt14d pt16d pt18d pt20d pt24d pt30d i/o 185 pt12c pt14c pt16c pt18b pt20a pt24a pt29a i/o 186 pt12b pt14a pt16a pt18a pt19d pt23d pt28d i/o 187 pt12a pt13d pt15d pt17d pt19a pt23a pt28a i/o-rdy/rclk 188 v ss see note see note v ss v ss v ss v ss v ss 189 pt11d pt13b pt15b pt16d pt17d pt21d pt26d i/o 190 pt11c pt13a pt15a pt16c pt17c pt21c pt26c i/o 191 pt11b pt12d pt14d pt16a pt17a pt21a pt26a i/o 192 pt11a pt12c pt13d pt15d pt16d pt20d pt25d i/o-d7 193 pt10d pt12a pt13b pt14d pt15d pt19d pt24d i/o-v dd 5 194 pt10c pt11d pt13a pt14a pt15a pt19a pt23d i/o 195 pt10b pt11c pt12d pt13d pt14d pt18d pt22d i/o 196 pt10a pt11b pt12b pt13b pt14b pt18b pt21d i/o-d6 197 v dd v dd v dd v dd v dd v dd v dd v dd 198 pt9d pt10d pt11d pt12d pt13d pt17d pt20d i/o 199 pt9c pt10c pt11c pt12c pt13c pt17a pt20a i/o 200 pt9b pt10b pt11b pt12b pt13b pt16d pt19d i/o 201 pt9a pt10a pt11a pt12a pt13a pt16a pt19a i/o-d5 202 pt8d pt9d pt10d pt11d pt12d pt15d pt18d i/o 203 pt8c pt9c pt10c pt11c pt12c pt15a pt18a i/o 204 pt8b pt9b pt10b pt11b pt12b pt14d pt17d i/o 205 pt8a pt9a pt10a pt11a pt12a pt14a pt17a i/o-d4 206 v ss v ss v ss v ss v ss v ss v ss v ss 207 pt7d pt8d pt9d pt10d pt11d pt13d pt16d i/o 208 pt7c pt8c pt9c pt10c pt11c pt13c pt16c i/o 209 pt7b pt8b pt9b pt10b pt11b pt13b pt16b i/o 210 pt7a pt8a pt9a pt10a pt11a pt13a pt16a i/o-d3 pin information (continued) table 24. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 240-pin sqfp/sqfp2 pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2c/2t08a and or2c/2t10a do not have bond pads connected to 240-pin sqfp package pin numbers 113 and 188. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 91 211 v ss v ss v ss v ss v ss v ss v ss v ss 212 pt6d pt7d pt8d pt9d pt10d pt12d pt15d i/o 213 pt6c pt7c pt8c pt9c pt10c pt12c pt15c i/o 214 pt6b pt7b pt8b pt9b pt10b pt12b pt15b i/o-v dd 5 215 pt6a pt7a pt8a pt9a pt10a pt12a pt15a i/o-d2 216 v ss v ss v ss v ss v ss v ss v ss v ss 217 pt5d pt6d pt7d pt8d pt9d pt11d pt14d i/o-d1 218 pt5c pt6c pt7c pt8c pt9c pt11a pt14a i/o 219 pt5b pt6b pt7b pt8b pt9b pt10d pt13d i/o 220 pt5a pt6a pt7a pt8a pt9a pt10a pt13a i/o-d0/din 221 pt4d pt5d pt6d pt7d pt8d pt9d pt12d i/o 222 pt4c pt5c pt6c pt7c pt8c pt9a pt12a i/o 223 pt4b pt5b pt6b pt7b pt8b pt8d pt11d i/o 224 pt4a pt5a pt6a pt7a pt8a pt8a pt11a i/o-dout 225 v dd v dd v dd v dd v dd v dd v dd v dd 226 pt3d pt4d pt5d pt6d pt7d pt7d pt10d i/o 227 pt3c pt4c pt5a pt6a pt7a pt7a pt9a i/o 228 pt3b pt4b pt4d pt5c pt6c pt6c pt8a i/o 229 pt3a pt4a pt4a pt5a pt6a pt6a pt7a i/o-tdi 230 pt2d pt3d pt3d pt4d pt5d pt5d pt6d i/o 231 pt2c pt3c pt3c pt4a pt5a pt5a pt6a i/o 232 pt2b pt3b pt3b pt3d pt4d pt4d pt5d i/o 233 pt2a pt3a pt3a pt3a pt4a pt4a pt5a i/o-tms 234 v ss v ss v ss v ss v ss v ss v ss v ss 235 pt1d pt2d pt2d pt2c pt3a pt3a pt4a i/o 236 pt1c pt2a pt2a pt2a pt2a pt2a pt3a i/o 237 pt1b pt1d pt1d pt1d pt1d pt1d pt2d i/o 238 pt1a pt1a pt1a pt1a pt1a pt1a pt1a i/o-tck 239 v ss v ss v ss v ss v ss v ss v ss v ss 240 rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/ tdo rd_data/tdo pin information (continued) table 24. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2c/2t40a/b 240-pin sqfp/sqfp2 pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2c/2t08a and or2c/2t10a do not have bond pads connected to 240-pin sqfp package pin numbers 113 and 188. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 92 lucent technologies inc. pin information (continued) table 25. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, and or2c/2t15a/b 256-pin pbga pinout pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad function c2 pl1d pl1d pl1d pl1d pl1d i/o d2 pl1c pl1b pl1b pl1c pl1c i/o d3 pl1b pl1a pl1a pl1b pl1b i/o e4 pl1a pl2d pl2d pl2d pl2d i/o-a0 c1 pl2c pl2c pl2c pl2a i/o d1 pl2b pl2b pl2b pl3d i/o e3 pl2a pl2a pl2a pl3a i/o e2 pl2d pl3d pl3d pl3d pl4d i/o-v dd 5 e1 pl2c pl3c pl3c pl3a pl4a i/o f3 pl2b pl3b pl3b pl4d pl5d i/o g4 pl2a pl3a pl3a pl4a pl5a i/o-a1 f2 pl4d pl5d pl6d i/o f1 pl3d pl4d pl4a pl5a pl6a i/o-a2 g3 pl3c pl4c pl5c pl6d pl7d i/o g2 pl3b pl4b pl5b pl6b pl7b i/o g1 pl3a pl4a pl5a pl6a pl7a i/o-a3 h3 pl4d pl5d pl6d pl7d pl8d i/o h2 pl4c pl5c pl6c pl7c pl8c i/o h1 pl4b pl5b pl6b pl7b pl8b i/o j4 pl4a pl5a pl6a pl7a pl8a i/o-a4 j3 pl5d pl6d pl7d pl8d pl9d i/o-a5 j2 pl5c pl6c pl7c pl8c pl9c i/o j1 pl5b pl6b pl7b pl8b pl9b i/o k2 pl5a pl6a pl7a pl8a pl9a i/o-a6 k3 pl6d pl7d pl8d pl9d pl10d i/o k1 pl6c pl7c pl8c pl9c pl10c i/o l1 pl6b pl7b pl8b pl9b pl10b i/o l2 pl6a pl7a pl8a pl9a pl10a i/o-a7 l3 pl7d pl8d pl9d pl10d pl11d i/o l4 pl7c pl8c pl9c pl10c pl11c i/o-v dd 5 m1 pl7b pl8b pl9b pl10b pl11b i/o m2 pl7a pl8a pl9a pl10a pl11a i/o-a8 m3 pl8d pl9d pl10d pl11d pl12d i/o-a9 m4 pl8c pl9c pl10c pl11c pl12c i/o n1 pl8b pl9b pl10b pl11b pl12b i/o n2 pl8a pl9a pl10a pl11a pl12a i/o-a10 n3 pl9d pl10d pl11d pl12d pl13d i/o p1 pl9c pl10c pl11c pl12c pl13c i/o p2 pl9b pl10b pl11b pl12b pl13b i/o r1 pl9a pl10a pl11a pl12a pl13a i/o-a11 notes: the w3 pin on the 256-pin pbga package is unconnected for all devices listed in this table. the or2c/2t08a do not have bond pads connected to the 256-pin pbga package pins f2 and y17. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 4 x 4 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 93 p3 pl10d pl11d pl12d pl13d pl14d i/o-a12 r2 pl10c pl11c pl12c pl13b pl14b i/o t1 pl10b pl11b pl12b pl14d pl15d i/o p4 pl10a pl11a pl13d pl14b pl15b i/o-a13 r3 pl11d pl12d pl13b pl14a pl15a i/o t2 pl11c pl12c pl13a pl15d pl16d i/o u1 pl11b pl12b pl14d pl15b pl16b i/o t3 pl11a pl12a pl14c pl16d pl17d i/o-a14 u2 pl13d pl15d pl17d pl18d i/o-v dd 5 v1 pl12d pl13c pl15c pl17c pl18c i/o t4 pl12c pl13b pl15b pl17b pl18a i/o u3 pl12b pl13a pl15a pl17a pl19d i/o v2 pl14d pl16d pl18d pl19c i/o w1 pl14c pl16c pl18c pl19a i/o v3 pl14b pl16b pl18b pl20d i/o w2 pl12a pl14a pl16a pl18a pl20a i/o-a15 y1 cclk cclk cclk cclk cclk cclk y2 pb1a pb1a pb1a pb1a pb1a i/o-a16 w4 pb1c pb1c pb1c pb1d i/o v4 pb1b pb1d pb1d pb1d pb2a i/o u5 pb1c pb2a pb2a pb2a pb2d i/o-v dd 5 y3 pb1d pb2b pb2b pb2b pb3a i/o y4 pb2c pb2c pb2c pb3c i/o v5 pb2d pb2d pb2d pb3d i/o w5 pb2a pb3a pb3b pb3d pb4d i/o-a17 y5 pb2b pb3b pb4b pb4d pb5d i/o v6 pb2c pb3c pb4c pb5a pb6a i/o u7 pb2d pb3d pb4d pb5b pb6b i/o w6 pb3a pb4a pb5a pb5d pb6d i/o y6 pb3b pb4b pb5b pb6a pb7a i/o v7 pb3c pb4c pb5c pb6b pb7b i/o w7 pb3d pb4d pb5d pb6d pb7d i/o y7 pb4a pb5a pb6a pb7a pb8a i/o v8 pb4b pb5b pb6b pb7b pb8b i/o w8 pb4c pb5c pb6c pb7c pb8c i/o y8 pb4d pb5d pb6d pb7d pb8d i/o u9 pb5a pb6a pb7a pb8a pb9a i/o v9 pb5b pb6b pb7b pb8b pb9b i/o w9 pb5c pb6c pb7c pb8c pb9c i/o y9 pb5d pb6d pb7d pb8d pb9d i/o pin information (continued) table 25. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, and or2c/2t15a/b 256-pin pbga pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad function notes: the w3 pin on the 256-pin pbga package is unconnected for all devices listed in this table. the or2c/2t08a do not have bond pads connected to the 256-pin pbga package pins f2 and y17. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 4 x 4 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet orca series 2 fpgas june 1999 94 lucent technologies inc. w10 pb6a pb7a pb8a pb9a pb10a i/o v10 pb6b pb7b pb8b pb9b pb10b i/o y10 pb6c pb7c pb8c pb9c pb10c i/o y11 pb6d pb7d pb8d pb9d pb10d i/o w11 pb7a pb8a pb9a pb10a pb11a i/o v11 pb7b pb8b pb9b pb10b pb11b i/o u11 pb7c pb8c pb9c pb10c pb11c i/o y12 pb7d pb8d pb9d pb10d pb11d i/o w12 pb8a pb9a pb10a pb11a pb12a i/o-v dd 5 v12 pb8b pb9b pb10b pb11b pb12b i/o u12 pb8c pb9c pb10c pb11c pb12c i/o y13 pb8d pb9d pb10d pb11d pb12d i/o w13 pb9a pb10a pb11a pb12a pb13a i/o-hdc v13 pb9b pb10b pb11b pb12b pb13b i/o y14 pb9c pb10c pb11c pb12c pb13c i/o w14 pb9d pb10d pb11d pb12d pb13d i/o y15 pb10a pb11a pb12a pb13a pb14a i/o- ldc v14 pb10b pb11b pb12c pb13b pb14b i/o w15 pb10c pb11c pb12d pb13c pb14c i/o y16 pb10d pb11d pb13a pb13d pb14d i/o u14 pb12a pb13b pb14a pb15a i/o v15 pb12b pb13c pb14d pb15d i/o w16 pb11a pb12c pb13d pb15a pb16a i/o- init y17 pb14a pb15d pb16d i/o v16 pb12d pb14b pb16a pb17a i/o-v dd 5 w17 pb11b pb13a pb15a pb16d pb17d i/o y18 pb11c pb13b pb15b pb17a pb18a i/o u16 pb11d pb13c pb15c pb17c pb18d i/o v17 pb12a pb13d pb15d pb17d pb19a i/o w18 pb12b pb14a pb16a pb18a pb19d i/o y19 pb12c pb14b pb16b pb18b pb20a i/o v18 pb12d pb14c pb16c pb18c pb20b i/o w19 pb14d pb16d pb18d pb20d i/o y20 done done done done done done w20 reset reset reset reset reset reset v19 prgm prgm prgm prgm prgm prgm u19 pr12a pr14a pr16a pr18a pr20a i/o-m0 u18 pr14c pr16c pr18c pr20d i/o t17 pr14d pr16d pr18d pr19a i/o v20 pr13a pr15a pr17a pr19d i/o pin information (continued) table 25. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, and or2c/2t15a/b 256-pin pbga pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad function notes: the w3 pin on the 256-pin pbga package is unconnected for all devices listed in this table. the or2c/2t08a do not have bond pads connected to the 256-pin pbga package pins f2 and y17. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 4 x 4 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 95 u20 pr12b pr13b pr15b pr17b pr18a i/o t18 pr12c pr13c pr15c pr17c pr18b i/o t19 pr12d pr13d pr15d pr17d pr18d i/o t20 pr11a pr12a pr14a pr16a pr17a i/o r18 pr11b pr12b pr14c pr16d pr17d i/o p17 pr11c pr12c pr14d pr15a pr16a i/o r19 pr11d pr12d pr13a pr15c pr16c i/o r20 pr10a pr11a pr13b pr15d pr16d i/o-m1 p18 pr10b pr11b pr13c pr14a pr15a i/o p19 pr10c pr11c pr12a pr14d pr15d i/o-v dd 5 p20 pr10d pr11d pr12b pr13a pr14a i/o n18 pr9a pr10a pr11a pr12a pr13a i/o-m2 n19 pr9b pr10b pr11b pr12b pr13b i/o n20 pr9c pr10c pr11c pr12c pr13c i/o m17 pr9d pr10d pr11d pr12d pr13d i/o m18 pr8a pr9a pr10a pr11a pr12a i/o-m3 m19 pr8b pr9b pr10b pr11b pr12b i/o m20 pr8c pr9c pr10c pr11c pr12c i/o l19 pr8d pr9d pr10d pr11d pr12d i/o l18 pr7a pr8a pr9a pr10a pr11a i/o l20 pr7b pr8b pr9b pr10b pr11b i/o k20 pr7c pr8c pr9c pr10c pr11c i/o k19 pr7d pr8d pr9d pr10d pr11d i/o k18 pr6a pr7a pr8a pr9a pr10a i/o k17 pr6b pr7b pr8b pr9b pr10b i/o j20 pr6c pr7c pr8c pr9c pr10c i/o j19 pr6d pr7d pr8d pr9d pr10d i/o j18 pr5a pr6a pr7a pr8a pr9a i/o-v dd 5 j17 pr5b pr6b pr7b pr8b pr9b i/o h20 pr5c pr6c pr7c pr8c pr9c i/o h19 pr5d pr6d pr7d pr8d pr9d i/o h18 pr4a pr5a pr6a pr7a pr8a i/o-cs1 g20 pr4b pr5b pr6b pr7b pr8b i/o g19 pr4c pr5c pr6c pr7c pr8c i/o f20 pr4d pr5d pr6d pr7d pr8d i/o g18 pr3a pr4a pr5a pr6a pr7a i/o- cs0 f19 pr3b pr4b pr4b pr6b pr7b i/o e20 pr3c pr4c pr4c pr5b pr6b i/o g17 pr3d pr4d pr4d pr5d pr6d i/o f18 pr2a pr3a pr3a pr4a pr5a i/o- rd pin information (continued) table 25. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, and or2c/2t15a/b 256-pin pbga pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad function notes: the w3 pin on the 256-pin pbga package is unconnected for all devices listed in this table. the or2c/2t08a do not have bond pads connected to the 256-pin pbga package pins f2 and y17. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 4 x 4 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet orca series 2 fpgas june 1999 96 lucent technologies inc. e19 pr2b pr3b pr3b pr4b pr5b i/o d20 pr2c pr3c pr3c pr4d pr5d i/o e18 pr2d pr3d pr3d pr3a pr4a i/o-v dd 5 d19 pr1a pr2a pr2a pr2a pr3a i/o- wr c20 pr1b pr2b pr2b pr2b pr3b i/o e17 pr1c pr2c pr2c pr2c pr2a i/o d18 pr1d pr2d pr2d pr2d pr2d i/o c19 pr1a pr1a pr1a pr1a i/o b20 pr1b pr1b pr1b pr1b i/o c18 pr1c pr1c pr1c pr1c i/o b19 pr1d pr1d pr1d pr1d i/o a20 rd_cfgn rd_cfgn rd_cfgn rd_cfgn rd_cfgn rd_cfgn a19 pt14d pt16d pt18d pt20d i/o b18 pt12d pt14c pt16c pt18c pt20c i/o b17 pt12c pt14b pt16b pt18b pt20a i/o c17 pt12b pt14a pt16a pt18a pt19d i/o d16 pt12a pt13d pt15d pt17d pt19a i/o- rdy/rclk a18 pt13c pt15c pt17a pt18a i/o a17 pt11d pt13b pt15b pt16d pt17d i/o c16 pt11c pt13a pt15a pt16c pt17c i/o b16 pt11b pt12d pt14d pt16a pt17a i/o a16 pt11a pt12c pt13d pt15d pt16d i/o-d7 c15 pt12b pt13c pt15a pt16a i/o d14 pt10d pt12a pt13b pt14d pt15d i/o-v dd 5 b15 pt10c pt11d pt13a pt14a pt15a i/o a15 pt10b pt11c pt12d pt13d pt14d i/o c14 pt10a pt11b pt12b pt13b pt14b i/o-d6 b14 pt9d pt11a pt12a pt13a pt14a i/o a14 pt9c pt10d pt11d pt12d pt13d i/o c13 pt10c pt11c pt12c pt13c i/o b13 pt9b pt10b pt11b pt12b pt13b i/o a13 pt9a pt10a pt11a pt12a pt13a i/o-d5 d12 pt8d pt9d pt10d pt11d pt12d i/o c12 pt8c pt9c pt10c pt11c pt12c i/o b12 pt8b pt9b pt10b pt11b pt12b i/o a12 pt8a pt9a pt10a pt11a pt12a i/o-d4 b11 pt7d pt8d pt9d pt10d pt11d i/o c11 pt7c pt8c pt9c pt10c pt11c i/o a11 pt7b pt8b pt9b pt10b pt11b i/o a10 pt7a pt8a pt9a pt10a pt11a i/o-d3 pin information (continued) table 25. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, and or2c/2t15a/b 256-pin pbga pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad function notes: the w3 pin on the 256-pin pbga package is unconnected for all devices listed in this table. the or2c/2t08a do not have bond pads connected to the 256-pin pbga package pins f2 and y17. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 4 x 4 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 97 b10 pt6d pt7d pt8d pt9d pt10d i/o c10 pt6c pt7c pt8c pt9c pt10c i/o d10 pt6b pt7b pt8b pt9b pt10b i/o-v dd 5 a9 pt6a pt7a pt8a pt9a pt10a i/o-d2 b9 pt5d pt6d pt7d pt8d pt9d i/o-d1 c9 pt5c pt6c pt7c pt8c pt9c i/o d9 pt5b pt6b pt7b pt8b pt9b i/o a8 pt5a pt6a pt7a pt8a pt9a i/o-d0/din b8 pt4d pt5d pt6d pt7d pt8d i/o c8 pt4c pt5c pt6c pt7c pt8c i/o a7 pt4b pt5b pt6b pt7b pt8b i/o b7 pt4a pt5a pt6a pt7a pt8a i/o-dout a6 pt3d pt4d pt5d pt6d pt7d i/o c7 pt3c pt4c pt5a pt6a pt7a i/o b6 pt3b pt4b pt4d pt5c pt6c i/o a5 pt3a pt4a pt4a pt5a pt6a i/o-tdi d7 pt2d pt3d pt3d pt4d pt5d i/o c6 pt2c pt3c pt3c pt4a pt5a i/o-v dd 5 b5 pt2b pt3b pt3b pt3d pt4d i/o a4 pt2a pt3a pt3a pt3a pt4a i/o-tms c5 pt2d pt2d pt2d pt3d i/o b4 pt1d pt2c pt2c pt2c pt3a i/o a3 pt1c pt2b pt2b pt2b pt2d i/o d5 pt1b pt2a pt2a pt2a pt2a i/o c4 pt1d pt1d pt1d pt1d i/o b3 pt1c pt1c pt1c pt1c i/o b2 pt1b pt1b pt1b pt1b i/o a2 pt1a pt1a pt1a pt1a pt1a i/o-tck c3 rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo a1 v ss v ss v ss v ss v ss v ss d4 v ss v ss v ss v ss v ss v ss d8 v ss v ss v ss v ss v ss v ss d13 v ss v ss v ss v ss v ss v ss d17 v ss v ss v ss v ss v ss v ss h4 v ss v ss v ss v ss v ss v ss h17 v ss v ss v ss v ss v ss v ss n4 v ss v ss v ss v ss v ss v ss n17 v ss v ss v ss v ss v ss v ss u4 v ss v ss v ss v ss v ss v ss pin information (continued) table 25. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, and or2c/2t15a/b 256-pin pbga pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad function notes: the w3 pin on the 256-pin pbga package is unconnected for all devices listed in this table. the or2c/2t08a do not have bond pads connected to the 256-pin pbga package pins f2 and y17. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 4 x 4 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet orca series 2 fpgas june 1999 98 lucent technologies inc. u8 v ss v ss v ss v ss v ss v ss u13 v ss v ss v ss v ss v ss v ss u17 v ss v ss v ss v ss v ss v ss b1 v dd v dd v dd v dd v dd v dd d6 v dd v dd v dd v dd v dd v dd d11 v dd v dd v dd v dd v dd v dd d15 v dd v dd v dd v dd v dd v dd f4 v dd v dd v dd v dd v dd v dd f17 v dd v dd v dd v dd v dd v dd k4 v dd v dd v dd v dd v dd v dd l17 v dd v dd v dd v dd v dd v dd r4 v dd v dd v dd v dd v dd v dd r17 v dd v dd v dd v dd v dd v dd u6 v dd v dd v dd v dd v dd v dd u10 v dd v dd v dd v dd v dd v dd u15 v dd v dd v dd v dd v dd v dd w3 no connect j10 v ss v ss v ss v ss v ss v ss etc j11 v ss v ss v ss v ss v ss v ss etc j12 v ss v ss v ss v ss v ss v ss etc j9 v ss v ss v ss v ss v ss v ss etc k10 v ss v ss v ss v ss v ss v ss etc k11 v ss v ss v ss v ss v ss v ss etc k12 v ss v ss v ss v ss v ss v ss etc k9 v ss v ss v ss v ss v ss v ss etc l10 v ss v ss v ss v ss v ss v ss etc l11 v ss v ss v ss v ss v ss v ss etc l12 v ss v ss v ss v ss v ss v ss etc l9 v ss v ss v ss v ss v ss v ss etc m10 v ss v ss v ss v ss v ss v ss etc m11 v ss v ss v ss v ss v ss v ss etc m12 v ss v ss v ss v ss v ss v ss etc m9 v ss v ss v ss v ss v ss v ss etc pin information (continued) table 25. or2c/2t06a, or2c/2t08a, or2c/2t10a, or2c/2t12a, and or2c/2t15a/b 256-pin pbga pinout (continued) pin 2c/2t06a pad 2c/2t08a pad 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad function notes: the w3 pin on the 256-pin pbga package is unconnected for all devices listed in this table. the or2c/2t08a do not have bond pads connected to the 256-pin pbga package pins f2 and y17. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 4 x 4 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 99 pin information (continued) table 26. or2c12a, or2c15a, or2c26a, and or2c40a 304-pin sqfp/sqfp2 pinout pin 2c12a pad 2c15a pad 2c26a pad 2c40a pad function 1v ss v ss v ss v ss v ss 2v dd v dd v dd v dd v dd 3v ss v ss v ss v ss v ss 4 pl1d pl1d pl1d pl1d i/o 5 pl1c pl1c pl1c pl1a i/o 6 pl1b pl1b pl1b pl2d i/o 7 pl1a pl1a pl1a pl2a i/o 8 pl2d pl2d pl2d pl3d i/o-a0 9 pl2c pl2a pl2a pl3a i/o 10 pl2b pl3d pl3d pl4d i/o 11 pl2a pl3a pl3a pl4a i/o 12 v ss v ss v ss v ss v ss 13 pl3d pl4d pl4d pl5d i/o 14 pl3a pl4a pl4a pl6d i/o 15 pl4d pl5d pl5d pl7d i/o 16 pl4a pl5a pl5a pl8d i/o-a1 17 pl5d pl6d pl6d pl9d i/o 18 pl5c pl6c pl6c pl9c i/o 19 pl5b pl6b pl6b pl9b i/o 20 pl5a pl6a pl6a pl9a i/o-a2 21 pl6d pl7d pl7d pl10d i/o 22 pl6c pl7c pl7c pl10c i/o 23 pl6b pl7b pl7b pl10b i/o 24 pl6a pl7a pl7a pl10a i/o-a3 25 v dd v dd v dd v dd v dd 26 pl7d pl8d pl8d pl11d i/o 27 pl7c pl8c pl8a pl11a i/o 28 pl7b pl8b pl9d pl12d i/o 29 pl7a pl8a pl9a pl12a i/o-a4 30 pl8d pl9d pl10d pl13d i/o-a5 31 pl8c pl9c pl10a pl13a i/o 32 pl8b pl9b pl11d pl14d i/o 33 pl8a pl9a pl11a pl14a i/o-a6 34 v ss v ss v ss v ss v ss 35 pl9d pl10d pl12d pl15d i/o 36 pl9c pl10c pl12c pl15c i/o 37 pl9b pl10b pl12b pl15b i/o 38 pl9a pl10a pl12a pl15a i/o-a7 39 v dd v dd v dd v dd v dd 40 pl10d pl11d pl13d pl16d i/o 41 pl10c pl11c pl13c pl16c i/o 42 pl10b pl11b pl13b pl16b i/o 43 pl10a pl11a pl13a pl16a i/o-a8 44 v ss v ss v ss v ss v ss note: the or2txxa and or2txxb series are not offered in the 304-pin sqfp/sqfp2 packages.
data sheet orca series 2 fpgas june 1999 100 lucent technologies inc. 45 pl11d pl12d pl14d pl17d i/o-a9 46 pl11c pl12c pl14a pl17a i/o 47 pl11b pl12b pl15d pl18d i/o 48 pl11a pl12a pl15a pl18a i/o-a10 49 pl12d pl13d pl16d pl19d i/o 50 pl12c pl13c pl16a pl19a i/o 51 pl12b pl13b pl17d pl20d i/o 52 pl12a pl13a pl17a pl20a i/o-a11 53 v dd v dd v dd v dd v dd 54 pl13d pl14d pl18d pl21d i/o-a12 55 pl13b pl14b pl18b pl21b i/o 56 pl13a pl14a pl18a pl21a i/o 57 pl14d pl15d pl19d pl22d i/o 58 pl14b pl15b pl19b pl22b i/o-a13 59 pl14a pl15a pl19a pl22a i/o 60 pl15d pl16d pl20d pl23d i/o 61 pl15b pl16b pl20b pl24d i/o 62 pl15a pl16a pl20a pl25d i/o 63 pl16d pl17d pl21d pl25a i/o-a14 64 pl16a pl17a pl21a pl26a i/o 65 v ss v ss v ss v ss v ss 66 pl17d pl18d pl22d pl27d i/o 67 pl17c pl18c pl22c pl27c i/o 68 pl17b pl18a pl22a pl27a i/o 69 pl17a pl19d pl23d pl28d i/o 70 pl18d pl19c pl23c pl28c i/o 71 pl18c pl19a pl23a pl28a i/o 72 pl18b pl20d pl24d pl29a i/o 73 pl18a pl20a pl24a pl30a i/o-a15 74 v ss v ss v ss v ss v ss 75 cclk cclk cclk cclk cclk 76 v dd v dd v dd v dd v dd 77 v ss v ss v ss v ss v ss 78 v dd v dd v dd v dd v dd 79 v ss v ss v ss v ss v ss 80 pb1a pb1a pb1a pb1a i/o-a16 81 pb1b pb1c pb1c pb2a i/o 82 pb1c pb1d pb1d pb2d i/o 83 pb1d pb2a pb2a pb3a i/o 84 pb2a pb2d pb2d pb3d i/o 85 pb2b pb3a pb3a pb4a i/o 86 pb2c pb3c pb3c pb4c i/o 87 pb2d pb3d pb3d pb4d i/o 88 v ss v ss v ss v ss v ss 89 pb3a pb4a pb4a pb5a i/o pin information (continued) table 26. or2c12a, or2c15a, or2c26a, and or2c40a 304-pin sqfp/sqfp2 pinout (continued) pin 2c12a pad 2c15a pad 2c26a pad 2c40a pad function note: the or2txxa and or2txxb series are not offered in the 304-pin sqfp/sqfp2 packages.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 101 90 pb3d pb4d pb4d pb5d i/o-a17 91 pb4a pb5a pb5a pb6a i/o 92 pb4d pb5d pb5d pb6d i/o 93 pb5a pb6a pb6a pb7a i/o 94 pb5b pb6b pb6b pb7d i/o 95 pb5c pb6c pb6c pb8a i/o 96 pb5d pb6d pb6d pb8d i/o 97 pb6a pb7a pb7a pb9a i/o 98 pb6b pb7b pb7b pb9d i/o 99 pb6c pb7c pb7c pb10a i/o 100 pb6d pb7d pb7d pb10d i/o 101 v dd v dd v dd v dd v dd 102 pb7a pb8a pb8a pb11a i/o 103 pb7b pb8b pb8d pb11d i/o 104 pb7c pb8c pb9a pb12a i/o 105 pb7d pb8d pb9d pb12d i/o 106 pb8a pb9a pb10a pb13a i/o 107 pb8b pb9b pb10d pb13d i/o 108 pb8c pb9c pb11a pb14a i/o 109 pb8d pb9d pb11d pb14d i/o 110 v ss v ss v ss v ss v ss 111 pb9a pb10a pb12a pb15a i/o 112 pb9b pb10b pb12b pb15b i/o 113 pb9c pb10c pb12c pb15c i/o 114 pb9d pb10d pb12d pb15d i/o 115 v ss v ss v ss v ss v ss 116 pb10a pb11a pb13a pb16a i/o 117 pb10b pb11b pb13b pb16b i/o 118 pb10c pb11c pb13c pb16c i/o 119 pb10d pb11d pb13d pb16d i/o 120 v ss v ss v ss v ss v ss 121 pb11a pb12a pb14a pb17a i/o 122 pb11b pb12b pb14d pb17d i/o 123 pb11c pb12c pb15a pb18a i/o 124 pb11d pb12d pb15d pb18d i/o 125 pb12a pb13a pb16a pb19a i/o-hdc 126 pb12b pb13b pb16d pb19d i/o 127 pb12c pb13c pb17a pb20a i/o 128 pb12d pb13d pb17d pb20d i/o 129 v dd v dd v dd v dd v dd 130 pb13a pb14a pb18a pb21a i/o- ldc 131 pb13b pb14b pb18b pb21d i/o 132 pb13c pb14c pb18c pb22a i/o 133 pb13d pb14d pb18d pb22d i/o 134 pb14a pb15a pb19a pb23a i/o pin information (continued) table 26. or2c12a, or2c15a, or2c26a, and or2c40a 304-pin sqfp/sqfp2 pinout (continued) pin 2c12a pad 2c15a pad 2c26a pad 2c40a pad function note: the or2txxa and or2txxb series are not offered in the 304-pin sqfp/sqfp2 packages.
data sheet orca series 2 fpgas june 1999 102 lucent technologies inc. 135 pb14b pb15b pb19b pb24a i/o 136 pb14d pb15d pb19d pb24d i/o 137 pb15a pb16a pb20a pb25a i/o- init 138 pb15d pb16d pb20d pb25d i/o 139 pb16a pb17a pb21a pb26a i/o 140 pb16d pb17d pb21d pb26d i/o 141 v ss v ss v ss v ss v ss 142 pb17a pb18a pb22a pb27a i/o 143 pb17b pb18b pb22b pb27b i/o 144 pb17c pb18d pb22d pb27d i/o 145 pb17d pb19a pb23a pb28a i/o 146 pb18a pb19d pb23d pb28d i/o 147 pb18b pb20a pb24a pb29a i/o 148 pb18c pb20b pb24b pb29d i/o 149 pb18d pb20d pb24d pb30d i/o 150 v ss v ss v ss v ss v ss 151 done done done done done 152 v dd v dd v dd v dd v dd 153 v ss v ss v ss v ss v ss 154 reset reset reset reset reset 155 prgm prgm prgm prgm prgm 156 pr18a pr20a pr24a pr30a i/o-m0 157 pr18b pr20c pr24c pr29a i/o 158 pr18c pr20d pr24d pr29d i/o 159 pr18d pr19a pr23a pr28a i/o 160 pr17a pr19d pr23d pr28d i/o 161 pr17b pr18a pr22a pr27a i/o 162 pr17c pr18b pr22b pr27b i/o 163 pr17d pr18d pr22d pr27d i/o 164 v ss v ss v ss v ss v ss 165 pr16a pr17a pr21a pr26a i/o 166 pr16d pr17d pr21d pr25a i/o 167 pr15a pr16a pr20a pr24a i/o 168 pr15c pr16c pr20c pr24d i/o 169 pr15d pr16d pr20d pr23d i/o-m1 170 pr14a pr15a pr19a pr22a i/o 171 pr14c pr15c pr19c pr22c i/o 172 pr14d pr15d pr19d pr22d i/o 173 pr13a pr14a pr18a pr21a i/o 174 pr13c pr14c pr18c pr21c i/o 175 pr13d pr14d pr18d pr21d i/o 176 v dd v dd v dd v dd v dd 177 pr12a pr13a pr17a pr20a i/o-m2 178 pr12b pr13b pr17d pr20d i/o 179 pr12c pr13c pr16a pr19a i/o pin information (continued) table 26. or2c12a, or2c15a, or2c26a, and or2c40a 304-pin sqfp/sqfp2 pinout (continued) pin 2c12a pad 2c15a pad 2c26a pad 2c40a pad function note: the or2txxa and or2txxb series are not offered in the 304-pin sqfp/sqfp2 packages.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 103 180 pr12d pr13d pr16d pr19d i/o 181 pr11a pr12a pr15a pr18a i/o-m3 182 pr11b pr12b pr15d pr18d i/o 183 pr11c pr12c pr14a pr17a i/o 184 pr11d pr12d pr14d pr17d i/o 185 v ss v ss v ss v ss v ss 186 pr10a pr11a pr13a pr16a i/o 187 pr10b pr11b pr13b pr16b i/o 188 pr10c pr11c pr13c pr16c i/o 189 pr10d pr11d pr13d pr16d i/o 190 v dd v dd v dd v dd v dd 191 pr9a pr10a pr12a pr15a i/o 192 pr9b pr10b pr12b pr15b i/o 193 pr9c pr10c pr12c pr15c i/o 194 pr9d pr10d pr12d pr15d i/o 195 v ss v ss v ss v ss v ss 196 pr8a pr9a pr11a pr14a i/o 197 pr8b pr9b pr11d pr14d i/o 198 pr8c pr9c pr10a pr13a i/o 199 pr8d pr9d pr10d pr13d i/o 200 pr7a pr8a pr9a pr12a i/o-cs1 201 pr7b pr8b pr9d pr12d i/o 202 pr7c pr8c pr8a pr11a i/o 203 pr7d pr8d pr8d pr11d i/o 204 v dd v dd v dd v dd v dd 205 pr6a pr7a pr7a pr10a i/o- cs0 206 pr6b pr7b pr7b pr10b i/o 207 pr6c pr7c pr7c pr10c i/o 208 pr6d pr7d pr7d pr10d i/o 209 pr5a pr6a pr6a pr9a i/o 210 pr5b pr6b pr6b pr9b i/o 211 pr5c pr6c pr6c pr9c i/o 212 pr5d pr6d pr6d pr9d i/o 213 pr4a pr5a pr5a pr8a i/o- rd 214 pr4b pr5b pr5b pr7a i/o 215 pr4d pr5d pr5d pr6a i/o 216 pr3a pr4a pr4a pr5a i/o 217 v ss v ss v ss v ss v ss 218 pr2a pr3a pr3a pr4a i/o- wr 219 pr2b pr3b pr3b pr4b i/o 220 pr2c pr2a pr2a pr3a i/o 221 pr2d pr2d pr2d pr3d i/o 222 pr1a pr1a pr1a pr2a i/o 223 pr1b pr1b pr1b pr2d i/o 224 pr1c pr1c pr1c pr1a i/o pin information (continued) table 26. or2c12a, or2c15a, or2c26a, and or2c40a 304-pin sqfp/sqfp2 pinout (continued) pin 2c12a pad 2c15a pad 2c26a pad 2c40a pad function note: the or2txxa and or2txxb series are not offered in the 304-pin sqfp/sqfp2 packages.
data sheet orca series 2 fpgas june 1999 104 lucent technologies inc. 225 pr1d pr1d pr1d pr1d i/o 226 v ss v ss v ss v ss v ss 227 rd_cfgn rd_cfgn rd_cfgn rd_cfgn rd_cfgn 228 v dd v dd v dd v dd v dd 229 v ss v ss v ss v ss v ss 230 v dd v dd v dd v dd v dd 231 v ss v ss v ss v ss v ss 232 pt18d pt20d pt24d pt30d i/o 233 pt18c pt20c pt24c pt30a i/o 234 pt18b pt20a pt24a pt29a i/o 235 pt18a pt19d pt23d pt28d i/o 236 pt17d pt19a pt23a pt28a i/o-rdy/rclk 237 pt17c pt18d pt22d pt27d i/o 238 pt17b pt18c pt22c pt27c i/o 239 pt17a pt18a pt22a pt27a i/o 240 v ss v ss v ss v ss v ss 241 pt16d pt17d pt21d pt26d i/o 242 pt16c pt17c pt21c pt26c i/o 243 pt16a pt17a pt21a pt26a i/o 244 pt15d pt16d pt20d pt25d i/o-d7 245 pt15a pt16a pt20a pt25a i/o 246 pt14d pt15d pt19d pt24d i/o 247 pt14a pt15a pt19a pt23d i/o 248 pt13d pt14d pt18d pt22d i/o 249 pt13c pt14c pt18c pt22a i/o 250 pt13b pt14b pt18b pt21d i/o-d6 251 pt13a pt14a pt18a pt21a i/o 252 v dd v dd v dd v dd v dd 253 pt12d pt13d pt17d pt20d i/o 254 pt12c pt13c pt17a pt20a i/o 255 pt12b pt13b pt16d pt19d i/o 256 pt12a pt13a pt16a pt19a i/o-d5 257 pt11d pt12d pt15d pt18d i/o 258 pt11c pt12c pt15a pt18a i/o 259 pt11b pt12b pt14d pt17d i/o 260 pt11a pt12a pt14a pt17a i/o-d4 261 v ss v ss v ss v ss v ss 262 pt10d pt11d pt13d pt16d i/o 263 pt10c pt11c pt13c pt16c i/o 264 pt10b pt11b pt13b pt16b i/o 265 pt10a pt11a pt13a pt16a i/o-d3 266 v ss v ss v ss v ss v ss 267 pt9d pt10d pt12d pt15d i/o 268 pt9c pt10c pt12c pt15c i/o 269 pt9b pt10b pt12b pt15b i/o pin information (continued) table 26. or2c12a, or2c15a, or2c26a, and or2c40a 304-pin sqfp/sqfp2 pinout (continued) pin 2c12a pad 2c15a pad 2c26a pad 2c40a pad function note: the or2txxa and or2txxb series are not offered in the 304-pin sqfp/sqfp2 packages.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 105 270 pt9a pt10a pt12a pt15a i/o-d2 271 v ss v ss v ss v ss v ss 272 pt8d pt9d pt11d pt14d i/o-d1 273 pt8c pt9c pt11a pt14a i/o 274 pt8b pt9b pt10d pt13d i/o 275 pt8a pt9a pt10a pt13a i/o-d0/din 276 pt7d pt8d pt9d pt12d i/o 277 pt7c pt8c pt9a pt12a i/o 278 pt7b pt8b pt8d pt11d i/o 279 pt7a pt8a pt8a pt11a i/o-dout 280 v dd v dd v dd v dd v dd 281 pt6d pt7d pt7d pt10d i/o 282 pt6c pt7c pt7c pt10a i/o 283 pt6b pt7b pt7b pt9d i/o 284 pt6a pt7a pt7a pt9a i/o 285 pt5d pt6d pt6d pt8d i/o 286 pt5c pt6c pt6c pt8a i/o 287 pt5b pt6b pt6b pt7d i/o 288 pt5a pt6a pt6a pt7a i/o-tdi 289 pt4d pt5d pt5d pt6d i/o 290 pt4a pt5a pt5a pt6a i/o 291 pt3d pt4d pt4d pt5d i/o 292 pt3a pt4a pt4a pt5a i/o-tms 293 v ss v ss v ss v ss v ss 294 pt2d pt3d pt3d pt4d i/o 295 pt2c pt3a pt3a pt4a i/o 296 pt2b pt2d pt2d pt3d i/o 297 pt2a pt2a pt2a pt3a i/o 298 pt1d pt1d pt1d pt2d i/o 299 pt1c pt1c pt1c pt2a i/o 300 pt1b pt1b pt1b pt1d i/o 301 pt1a pt1a pt1a pt1a i/o-tck 302 v ss v ss v ss v ss v ss 303 rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo 304 v dd v dd v dd v dd v dd pin information (continued) table 26. or2c12a, or2c15a, or2c26a, and or2c40a 304-pin sqfp/sqfp2 pinout (continued) pin 2c12a pad 2c15a pad 2c26a pad 2c40a pad function note: the or2txxa and or2txxb series are not offered in the 304-pin sqfp/sqfp2 packages.
data sheet orca series 2 fpgas june 1999 106 lucent technologies inc. pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function b1 pl1d pl1d pl1d pl1d pl1d i/o c2 pl1c pl1c pl1c pl1c pl1a i/o c1 pl1b pl1b pl1b pl1b pl2d i/o d2 pl1a pl1a pl1a pl1a pl2a i/o d3 pl2d pl2d pl2d pl2d pl3d i/o-a0 d1 pl2c pl2c pl2a pl2a pl3a i/o e2 pl2b pl2b pl3d pl3d pl4d i/o e4 pl3b pl3b pl4b i/o e3 pl2a pl2a pl3a pl3a pl4a i/o e1 pl3d pl3d pl4d pl4d v dd 5 i/o-v dd 5 f2 pl3c pl4c pl4c pl5c i/o g4 pl3c pl3b pl4b pl4b pl5b i/o f3 pl3a pl4a pl4a pl6d i/o f1 pl3b pl4d pl5d pl5d pl7d i/o g2 pl4c pl5c pl5c pl7c i/o g1 pl4b pl5b pl5b pl7b i/o g3 pl3a pl4a pl5a pl5a pl8d i/o-a1 h2 pl4d pl5d pl6d pl6d pl9d i/o j4 pl4c pl5c pl6c pl6c pl9c i/o h1 pl4b pl5b pl6b pl6b pl9b i/o h3 pl4a pl5a pl6a pl6a pl9a i/o-a2 j2 pl5d pl6d pl7d pl7d pl10d i/o j1 pl5c pl6c pl7c pl7c pl10c i/o k2 pl5b pl6b pl7b pl7b pl10b i/o j3 pl5a pl6a pl7a pl7a pl10a i/o-a3 k1 pl6d pl7d pl8d pl8d pl11d i/o k4 pl6c pl7c pl8c pl8a pl11a i/o l2 pl6b pl7b pl8b pl9d pl12d i/o k3 pl6a pl7a pl8a pl9a pl12a i/o-a4 l1 pl7d pl8d pl9d pl10d pl13d i/o-a5 m2 pl7c pl8c pl9c pl10a pl13a i/o m1 pl7b pl8b pl9b pl11d pl14d i/o l3 pl7a pl8a pl9a pl11a pl14a i/o-a6 n2 pl8d pl9d pl10d pl12d pl15d i/o m4 pl8c pl9c pl10c pl12c pl15c i/o n1 pl8b pl9b pl10b pl12b pl15b i/o m3 pl8a pl9a pl10a pl12a pl15a i/o-a7 p2 pl9d pl10d pl11d pl13d pl16d i/o notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 107 p4 pl9c pl10c pl11c pl13c v dd 5 i/o-v dd 5 p1 pl9b pl10b pl11b pl13b pl16b i/o n3 pl9a pl10a pl11a pl13a pl16a i/o-a8 r2 pl10d pl11d pl12d pl14d pl17d i/o-a9 p3 pl10c pl11c pl12c pl14a pl17a i/o r1 pl10b pl11b pl12b pl15d pl18d i/o t2 pl10a pl11a pl12a pl15a pl18a i/o-a10 r3 pl11d pl12d pl13d pl16d pl19d i/o t1 pl11c pl12c pl13c pl16a pl19a i/o r4 pl11b pl12b pl13b pl17d pl20d i/o u2 pl11a pl12a pl13a pl17a pl20a i/o-a11 t3 pl12d pl13d pl14d pl18d pl21d i/o-a12 u1 pl13c pl14c pl18c pl21c i/o u4 pl12c pl13b pl14b pl18b pl21b i/o v2 pl13a pl14a pl18a pl21a i/o u3 pl12b pl14d pl15d pl19d pl22d i/o v1 pl12a pl14c pl15c pl19c pl22c i/o w2 pl13d pl14b pl15b pl19b pl22b i/o-a13 w1 pl13c pl14a pl15a pl19a pl22a i/o v3 pl13b pl15d pl16d pl20d pl23d i/o y2 pl13a pl15c pl16c pl20c pl23c i/o w4 pl14d pl15b pl16b pl20b pl24d i/o y1 pl15a pl16a pl20a pl25d i/o w3 pl14c pl16d pl17d pl21d pl25a i/o-a14 aa2 pl14b pl16c pl17c pl21c pl26c i/o y4 pl14a pl16b pl17b pl21b pl26b i/o aa1 pl16a pl17a pl21a pl26a i/o y3 pl15d pl17d pl18d pl22d v dd 5 i/o-v dd 5 ab2 pl15c pl17c pl18c pl22c pl27c i/o ab1 pl15b pl17b pl18a pl22a pl27a i/o aa3 pl15a pl17a pl19d pl23d pl28d i/o ac2 pl16d pl18d pl19c pl23c pl28c i/o ab4 pl16c pl18c pl19a pl23a pl28a i/o ac1 pl16b pl18b pl20d pl24d pl29a i/o ab3 pl20c pl24c pl30c i/o ad2 pl20b pl24b pl30b i/o ac3 pl16a pl18a pl20a pl24a pl30a i/o-a15 ad1 cclk cclk cclk cclk pcclk cclk af2 pb1a pb1a pb1a pb1a pb1a i/o-a16 pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout (continued) pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet orca series 2 fpgas june 1999 108 lucent technologies inc. ae3 pb1b pb1b pb1b i/o af3 pb1b pb1b pb1c pb1c pb2a i/o ae4 pb1c pb1c pb1d pb1d pb2d i/o ad4 pb1d pb1d pb2a pb2a pb3a i/o af4 pb2a pb2a pb2d pb2d v dd 5 i/o-v dd 5 ae5 pb2b pb3a pb3a pb4a i/o ac5 pb2b pb2c pb3c pb3c pb4c i/o ad5 pb2d pb3d pb3d pb4d i/o af5 pb2c pb3a pb4a pb4a pb5a i/o ae6 pb2d pb3b pb4b pb4b pb5b i/o ac7 pb3a pb3c pb4c pb4c pb5c i/o ad6 pb3b pb3d pb4d pb4d pb5d i/o-a17 af6 pb4a pb5a pb5a pb6a i/o ae7 pb3c pb4b pb5b pb5b pb6b i/o af7 pb4c pb5c pb5c pb6c i/o ad7 pb3d pb4d pb5d pb5d pb6d i/o ae8 pb4a pb5a pb6a pb6a pb7a i/o ac9 pb4b pb5b pb6b pb6b pb7d i/o af8 pb4c pb5c pb6c pb6c pb8a i/o ad8 pb4d pb5d pb6d pb6d pb8d i/o ae9 pb5a pb6a pb7a pb7a pb9a i/o af9 pb5b pb6b pb7b pb7b pb9d i/o ae10 pb5c pb6c pb7c pb7c pb10a i/o ad9 pb5d pb6d pb7d pb7d pb10d i/o af10 pb6a pb7a pb8a pb8a pb11a i/o ac10 pb6b pb7b pb8b pb8d pb11d i/o ae11 pb6c pb7c pb8c pb9a pb12a i/o ad10 pb6d pb7d pb8d pb9d pb12d i/o af11 pb7a pb8a pb9a pb10a pb13a i/o ae12 pb7b pb8b pb9b pb10d pb13d i/o af12 pb7c pb8c pb9c pb11a pb14a i/o ad11 pb7d pb8d pb9d pb11d pb14d i/o ae13 pb8a pb9a pb10a pb12a pb15a i/o ac12 pb8b pb9b pb10b pb12b pb15b i/o af13 pb8c pb9c pb10c pb12c pb15c i/o ad12 pb8d pb9d pb10d pb12d pb15d i/o ae14 pb9a pb10a pb11a pb13a pb16a i/o ac14 pb9b pb10b pb11b pb13b pb16b i/o af14 pb9c pb10c pb11c pb13c pb16c i/o pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout (continued) pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 109 ad13 pb9d pb10d pb11d pb13d pb16d i/o ae15 pb10a pb11a pb12a pb14a v dd 5 i/o-v dd 5 ad14 pb10b pb11b pb12b pb14d pb17d i/o af15 pb10c pb11c pb12c pb15a pb18a i/o ae16 pb10d pb11d pb12d pb15d pb18d i/o ad15 pb11a pb12a pb13a pb16a pb19a i/o-hdc af16 pb11b pb12b pb13b pb16d pb19d i/o ac15 pb11c pb12c pb13c pb17a pb20a i/o ae17 pb11d pb12d pb13d pb17d pb20d i/o ad16 pb12a pb13a pb14a pb18a pb21a i/o- ldc af17 pb12b pb13b pb14b pb18b pb21d i/o ac17 pb12c pb13c pb14c pb18c pb22a i/o ae18 pb12d pb13d pb14d pb18d pb22d i/o ad17 pb13a pb14a pb15a pb19a pb23a i/o af18 pb13b pb14b pb15b pb19b pb24a i/o ae19 pb14c pb15c pb19c pb24c i/o af19 pb13c pb14d pb15d pb19d pb24d i/o ad18 pb13d pb15a pb16a pb20a pb25a i/o- init ae20 pb15b pb16b pb20b pb25b i/o ac19 pb14a pb15c pb16c pb20c pb25c i/o af20 pb15d pb16d pb20d pb25d i/o ad19 pb14b pb16a pb17a pb21a v dd 5 i/o-v dd 5 ae21 pb14c pb16b pb17b pb21b pb26b i/o ac20 pb14d pb16c pb17c pb21c pb26c i/o af21 pb15a pb16d pb17d pb21d pb26d i/o ad20 pb15b pb17a pb18a pb22a pb27a i/o ae22 pb15c pb17b pb18b pb22b pb27b i/o af22 pb15d pb17c pb18d pb22d pb27d i/o ad21 pb16a pb17d pb19a pb23a pb28a i/o ae23 pb19c pb23b pb28b i/o ac22 pb16b pb18a pb19d pb23d pb28d i/o af23 pb16c pb18b pb20a pb24a pb29a i/o ad22 pb16d pb18c pb20b pb24b pb29d i/o ae24 pb20c pb24c pb30c i/o ad23 pb18d pb20d pb24d pb30d i/o af24 done done done done pdone done ae26 reset reset reset reset presetn reset ad25 prgm prgm prgm prgm pprgmn prgm ad26 pr16a pr18a pr20a pr24a pr30a i/o-m0 pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout (continued) pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet orca series 2 fpgas june 1999 110 lucent technologies inc. ac25 pr16b pr18b pr20c pr24c pr29a i/o ac24 pr16c pr18c pr20d pr24d pr29d i/o ac26 pr16d pr18d pr19a pr23a pr28a i/o ab25 pr15a pr17a pr19d pr23d pr28d i/o ab23 pr15b pr17b pr18a pr22a pr27a i/o ab24 pr15c pr17c pr18b pr22b pr27b i/o ab26 pr15d pr17d pr18d pr22d pr27d i/o aa25 pr14a pr16a pr17a pr21a pr26a i/o y23 pr14b pr16b pr17b pr21b pr26b i/o aa24 pr14c pr16c pr17c pr21c pr26c i/o aa26 pr16d pr17d pr21d pr25a i/o y25 pr14d pr15a pr16a pr20a pr24a i/o y26 pr15b pr16b pr20b pr24b i/o y24 pr13a pr15c pr16c pr20c pr24d i/o w25 pr13b pr15d pr16d pr20d pr23d i/o-m1 v23 pr13c pr14a pr15a pr19a pr22a i/o w26 pr14b pr15b pr19b pr22b i/o w24 pr13d pr14c pr15c pr19c pr22c i/o v25 pr12a pr14d pr15d pr19d v dd 5 i/o-v dd 5 v26 pr12b pr13a pr14a pr18a pr21a i/o u25 pr13b pr14b pr18b pr21b i/o v24 pr12c pr13c pr14c pr18c pr21c i/o u26 pr12d pr13d pr14d pr18d pr21d i/o u23 pr11a pr12a pr13a pr17a pr20a i/o-m2 t25 pr11b pr12b pr13b pr17d pr20d i/o u24 pr11c pr12c pr13c pr16a pr19a i/o t26 pr11d pr12d pr13d pr16d pr19d i/o r25 pr10a pr11a pr12a pr15a pr18a i/o-m3 r26 pr10b pr11b pr12b pr15d pr18d i/o t24 pr10c pr11c pr12c pr14a pr17a i/o p25 pr10d pr11d pr12d pr14d pr17d i/o r23 pr9a pr10a pr11a pr13a pr16a i/o p26 pr9b pr10b pr11b pr13b pr16b i/o r24 pr9c pr10c pr11c pr13c pr16c i/o n25 pr9d pr10d pr11d pr13d pr16d i/o n23 pr8a pr9a pr10a pr12a pr15a i/o n26 pr8b pr9b pr10b pr12b pr15b i/o p24 pr8c pr9c pr10c pr12c pr15c i/o m25 pr8d pr9d pr10d pr12d pr15d i/o pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout (continued) pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 111 n24 pr7a pr8a pr9a pr11a v dd 5 i/o-v dd 5 m26 pr7b pr8b pr9b pr11d pr14d i/o l25 pr7c pr8c pr9c pr10a pr13a i/o m24 pr7d pr8d pr9d pr10d pr13d i/o l26 pr6a pr7a pr8a pr9a pr12a i/o-cs1 m23 pr6b pr7b pr8b pr9d pr12d i/o k25 pr6c pr7c pr8c pr8a pr11a i/o l24 pr6d pr7d pr8d pr8d pr11d i/o k26 pr5a pr6a pr7a pr7a pr10a i/o- cs0 k23 pr5b pr6b pr7b pr7b pr10b i/o j25 pr5c pr6c pr7c pr7c pr10c i/o k24 pr5d pr6d pr7d pr7d pr10d i/o j26 pr4a pr5a pr6a pr6a pr9a i/o h25 pr4b pr5b pr6b pr6b pr9b i/o h26 pr4c pr5c pr6c pr6c pr9c i/o j24 pr4d pr5d pr6d pr6d pr9d i/o g25 pr3a pr4a pr5a pr5a pr8a i/o- rd h23 pr3b pr4b pr5b pr5b pr7a i/o g26 pr4c pr5c pr5c pr7c i/o h24 pr3c pr4d pr5d pr5d pr6a i/o f25 pr3d pr3a pr4a pr4a v dd 5 i/o-v dd 5 g23 pr3b pr4b pr4b pr5b i/o f26 pr3c pr4c pr4c pr5c i/o g24 pr3d pr4d pr4d pr5d i/o e25 pr2a pr2a pr3a pr3a pr4a i/o- wr e26 pr2b pr2b pr3b pr3b pr4b i/o f24 pr3d pr3d pr4d i/o d25 pr2c pr2c pr2a pr2a pr3a i/o e23 pr2d pr2d pr2d pr2d pr3d i/o d26 pr1a pr1a pr1a pr1a pr2a i/o e24 pr1b pr1b pr1b pr1b pr2d i/o c25 pr1c pr1c pr1c pr1c pr1a i/o d24 pr1d pr1d pr1d pr1d pr1d i/o c26 rd_cfgn rd_cfgn rd_cfgn rd_cfgn rd_cfgn rd_cfgn a25 pt16d pt18d pt20d pt24d pt30d i/o b24 pt16c pt18c pt20c pt24c pt30a i/o a24 pt20b pt24b pt29b i/o b23 pt16b pt18b pt20a pt24a pt29a i/o c23 pt16a pt18a pt19d pt23d pt28d i/o pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout (continued) pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet orca series 2 fpgas june 1999 112 lucent technologies inc. a23 pt15d pt17d pt19a pt23a pt28a i/o-rdy/ rclk b22 pt15c pt17c pt18d pt22d pt27d i/o d22 pt15b pt17b pt18c pt22c pt27c i/o c22 pt15a pt17a pt18a pt22a pt27a i/o a22 pt14d pt16d pt17d pt21d pt26d i/o b21 pt14c pt16c pt17c pt21c pt26c i/o d20 pt14b pt16b pt17b pt21b pt26b i/o c21 pt14a pt16a pt17a pt21a pt26a i/o a21 pt13d pt15d pt16d pt20d pt25d i/o-d7 b20 pt15c pt16c pt20c pt25c i/o a20 pt13c pt15b pt16b pt20b pt25b i/o c20 pt15a pt16a pt20a pt25a i/o b19 pt13b pt14d pt15d pt19d v dd 5 i/o-v dd 5 d18 pt14c pt15c pt19c pt24c i/o a19 pt13a pt14b pt15b pt19b pt24b i/o c19 pt14a pt15a pt19a pt23d i/o b18 pt12d pt13d pt14d pt18d pt22d i/o a18 pt12c pt13c pt14c pt18c pt22a i/o b17 pt12b pt13b pt14b pt18b pt21d i/o-d6 c18 pt12a pt13a pt14a pt18a pt21a i/o a17 pt11d pt12d pt13d pt17d pt20d i/o d17 pt11c pt12c pt13c pt17a pt20a i/o b16 pt11b pt12b pt13b pt16d pt19d i/o c17 pt11a pt12a pt13a pt16a pt19a i/o-d5 a16 pt10d pt11d pt12d pt15d pt18d i/o b15 pt10c pt11c pt12c pt15a pt18a i/o a15 pt10b pt11b pt12b pt14d pt17d i/o c16 pt10a pt11a pt12a pt14a pt17a i/o-d4 b14 pt9d pt10d pt11d pt13d pt16d i/o d15 pt9c pt10c pt11c pt13c pt16c i/o a14 pt9b pt10b pt11b pt13b pt16b i/o c15 pt9a pt10a pt11a pt13a pt16a i/o-d3 b13 pt8d pt9d pt10d pt12d pt15d i/o d13 pt8c pt9c pt10c pt12c pt15c i/o a13 pt8b pt9b pt10b pt12b v dd 5 i/o-v dd 5 c14 pt8a pt9a pt10a pt12a pt15a i/o-d2 b12 pt7d pt8d pt9d pt11d pt14d i/o-d1 c13 pt7c pt8c pt9c pt11a pt14a i/o pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout (continued) pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 113 a12 pt7b pt8b pt9b pt10d pt13d i/o b11 pt7a pt8a pt9a pt10a pt13a i/o-d0/din c12 pt6d pt7d pt8d pt9d pt12d i/o a11 pt6c pt7c pt8c pt9a pt12a i/o d12 pt6b pt7b pt8b pt8d pt11d i/o b10 pt6a pt7a pt8a pt8a/ pt11a i/o-dout c11 pt5d pt6d pt7d pt7d pt10d i/o a10 pt5c pt6c pt7c pt7c pt10a i/o d10 pt5b pt6b pt7b pt7b pt9d i/o b9 pt5a pt6a pt7a pt7a pt9a i/o c10 pt4d pt5d pt6d pt6d pt8d i/o a9 pt4c pt5c pt6c pt6c pt8a i/o b8 pt4b pt5b pt6b pt6b pt7d i/o a8 pt4a pt5a pt6a pt6a pt7a i/o-tdi c9 pt4d pt5d pt5d pt6d i/o b7 pt3d pt4c pt5c pt5c pt6c i/o d8 pt4b pt5b pt5b pt6b i/o a7 pt3c pt4a pt5a pt5a v dd 5 i/o-v dd 5 c8 pt3d pt4d pt4d pt5d i/o b6 pt3b pt3c pt4c pt4c pt5c i/o d7 pt3b pt4b pt4b pt5b i/o a6 pt3a pt3a pt4a pt4a pt5a i/o-tms c7 pt2d pt2d pt3d pt3d pt4d i/o b5 pt2c pt2c pt3a pt3a pt4a i/o a5 pt2b pt2b pt2d pt2d pt3d i/o c6 pt2c pt2c pt3c i/o b4 pt2b pt2b pt3b i/o d5 pt2a pt2a pt2a pt2a pt3a i/o a4 pt1d pt1d pt1d pt1d pt2d i/o c5 pt1c pt1c pt1c pt1c pt2a i/o b3 pt1b pt1b pt1b pt1b pt1d i/o c4 pt1a pt1a pt1a pt1a pt1a i/o-tck a3 rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo rd_data/ tdo a1 v ss v ss v ss v ss v ss v ss a2 v ss v ss v ss v ss v ss v ss a26 v ss v ss v ss v ss v ss v ss ac13 v ss v ss v ss v ss v ss v ss ac18 v ss v ss v ss v ss v ss v ss ac23 v ss v ss v ss v ss v ss v ss pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout (continued) pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet orca series 2 fpgas june 1999 114 lucent technologies inc. ac4 v ss v ss v ss v ss v ss v ss ac8 v ss v ss v ss v ss v ss v ss ad24 v ss v ss v ss v ss v ss v ss ad3 v ss v ss v ss v ss v ss v ss ae1 v ss v ss v ss v ss v ss v ss ae2 v ss v ss v ss v ss v ss v ss ae25 v ss v ss v ss v ss v ss v ss af1 v ss v ss v ss v ss v ss v ss af25 v ss v ss v ss v ss v ss v ss af26 v ss v ss v ss v ss v ss v ss b2 v ss v ss v ss v ss v ss v ss b25 v ss v ss v ss v ss v ss v ss b26 v ss v ss v ss v ss v ss v ss c24 v ss v ss v ss v ss v ss v ss c3 v ss v ss v ss v ss v ss v ss d14 v ss v ss v ss v ss v ss v ss d19 v ss v ss v ss v ss v ss v ss d23 v ss v ss v ss v ss v ss v ss d4 v ss v ss v ss v ss v ss v ss d9 v ss v ss v ss v ss v ss v ss h4 v ss v ss v ss v ss v ss v ss j23 v ss v ss v ss v ss v ss v ss n4 v ss v ss v ss v ss v ss v ss p23 v ss v ss v ss v ss v ss v ss v4 v ss v ss v ss v ss v ss v ss w23 v ss v ss v ss v ss v ss v ss aa23 v dd v dd v dd v dd v dd v dd aa4 v dd v dd v dd v dd v dd v dd ac11 v dd v dd v dd v dd v dd v dd ac16 v dd v dd v dd v dd v dd v dd ac21 v dd v dd v dd v dd v dd v dd ac6 v dd v dd v dd v dd v dd v dd d11 v dd v dd v dd v dd v dd v dd d16 v dd v dd v dd v dd v dd v dd d21 v dd v dd v dd v dd v dd v dd d6 v dd v dd v dd v dd v dd v dd f23 v dd v dd v dd v dd v dd v dd f4 v dd v dd v dd v dd v dd v dd l23 v dd v dd v dd v dd v dd v dd pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout (continued) pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 115 l4 v dd v dd v dd v dd v dd v dd t23 v dd v dd v dd v dd v dd v dd t4 v dd v dd v dd v dd v dd v dd l11 v ss v ss v ss v ss v ss v ss etc l12 v ss v ss v ss v ss v ss v ss etc l13 v ss v ss v ss v ss v ss v ss etc l14 v ss v ss v ss v ss v ss v ss etc l15 v ss v ss v ss v ss v ss v ss etc l16 v ss v ss v ss v ss v ss v ss etc m11 v ss v ss v ss v ss v ss v ss etc m12 v ss v ss v ss v ss v ss v ss etc m13 v ss v ss v ss v ss v ss v ss etc m14 v ss v ss v ss v ss v ss v ss etc m15 v ss v ss v ss v ss v ss v ss etc m16 v ss v ss v ss v ss v ss v ss etc n11 v ss v ss v ss v ss v ss v ss etc n12 v ss v ss v ss v ss v ss v ss etc n13 v ss v ss v ss v ss v ss v ss etc n14 v ss v ss v ss v ss v ss v ss etc n15 v ss v ss v ss v ss v ss v ss etc n16 v ss v ss v ss v ss v ss v ss etc p11 v ss v ss v ss v ss v ss v ss etc p12 v ss v ss v ss v ss v ss v ss etc p13 v ss v ss v ss v ss v ss v ss etc p14 v ss v ss v ss v ss v ss v ss etc p15 v ss v ss v ss v ss v ss v ss etc p16 v ss v ss v ss v ss v ss v ss etc r11 v ss v ss v ss v ss v ss v ss etc r12 v ss v ss v ss v ss v ss v ss etc r13 v ss v ss v ss v ss v ss v ss etc r14 v ss v ss v ss v ss v ss v ss etc r15 v ss v ss v ss v ss v ss v ss etc r16 v ss v ss v ss v ss v ss v ss etc t11 v ss v ss v ss v ss v ss v ss etc t12 v ss v ss v ss v ss v ss v ss etc t13 v ss v ss v ss v ss v ss v ss etc t14 v ss v ss v ss v ss v ss v ss etc t15 v ss v ss v ss v ss v ss v ss etc t16 v ss v ss v ss v ss v ss v ss etc pin information (continued) table 27. or2c/2t10a, or2c/2t12a, or2c/2t15a/b, or2c/2t26a, and or2t40a/b 352-pin pbga pinout (continued) pin 2c/2t10a pad 2c/2t12a pad 2c/2t15a/b pad 2c/2t26a pad or2t40a/b pad function notes: the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series. the pins labeled v ss -etc are the 6 x 6 array of thermal balls located at the center of the package. the balls can be attached to the ground plane of the board for enhanced thermal capability (see table 29), or they can be left unconnected.
data sheet orca series 2 fpgas june 1999 116 lucent technologies inc. pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function e28 pl1d pl1d pl1d i/o d29 pl1c pl1c pl1a i/o d30 pl1b pl1b pl2d i/o d31 pl1a pl1a pl2a i/o f28 pl2d pl2d pl3d i/o-a0 e29 pl2c pl2c pl3c i/o e30 pl2b pl2b pl3b i/o e31 pl2a pl2a pl3a i/o f29 pl3d pl3d pl4d i/o f30 pl3c pl3c pl4c i/o f31 pl3b pl3b pl4b i/o h28 pl3a pl3a pl4a i/o g29 pl4d pl4d pl5d i/o-v dd 5 g30 pl4c pl4c pl5c i/o g31 pl4b pl4b pl5b i/o j28 pl4a pl4a pl6d i/o h29 pl5d pl5d pl7d i/o h30 pl5c pl5c pl7c i/o j29 pl5b pl5b pl7b i/o k28 pl5a pl5a pl8d i/o-a1 j30 pl6d pl6d pl9d i/o j31 pl6c pl6c pl9c i/o k29 pl6b pl6b pl9b i/o k30 pl6a pl6a pl9a i/o-a2 k31 pl7d pl7d pl10d i/o l29 pl7c pl7c pl10c i/o m28 pl7b pl7b pl10b i/o l30 pl7a pl7a pl10a i/o-a3 l31 pl8d pl11d i/o-v dd 5 m29 pl8d pl8c pl11c i/o n28 pl8c pl8a pl11a i/o m30 pl8b pl9d pl12d i/o n29 pl9c pl12c i/o n30 pl8a pl9a pl12a i/o-a4 p28 pl9d pl10d pl13d i/o-a5 n31 pl10c pl13c i/o p29 pl9c pl10a pl13a i/o p30 pl9b pl11d pl14d i/o p31 pl9a pl11a pl14a i/o-a6 r29 pl10d pl12d pl15d i/o r30 pl10c pl12c pl15c i/o r31 pl10b pl12b pl15b i/o t29 pl10a pl12a pl15a i/o-a7 notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 117 t28 pl11d pl13d pl16d i/o t30 pl11c pl13c pl16c i/o-v dd 5 u31 pl11b pl13b pl16b i/o u30 pl11a pl13a pl16a i/o-a8 u29 pl12d pl14d pl17d i/o-a9 v31 pl14c pl17c i/o v30 pl12c pl14a pl17a i/o v29 pl12b pl15d pl18d i/o w31 pl15c pl18c i/o v28 pl12a pl15a pl18a i/o-a10 w30 pl13d pl16d pl19d i/o w29 pl16c pl19c i/o y30 pl13c pl16a pl19a i/o w28 pl13b pl17d pl20d i/o y29 pl13a pl17a pl20a i/o-a11 aa31 pl14d pl18d pl21d i/o-a12 aa30 pl14c pl18c pl21c i/o y28 pl14b pl18b pl21b i/o aa29 pl14a pl18a pl21a i/o ab31 pl15d pl19d pl22d i/o ab30 pl15c pl19c pl22c i/o ab29 pl15b pl19b pl22b i/o-a13 ac31 pl15a pl19a pl22a i/o ac30 pl16d pl20d pl23d i/o ab28 pl16c pl20c pl23c i/o ac29 pl16b pl20b pl24d i/o ad30 pl16a pl20a pl25d i/o ad29 pl17d pl21d pl25a i/o-a14 ac28 pl17c pl21c pl26c i/o ae31 pl17b pl21b pl26b i/o ae30 pl17a pl21a pl26a i/o ae29 pl18d pl22d pl27d i/o-v dd 5 ad28 pl18c pl22c pl27c i/o af31 pl18b pl22b pl27b i/o af30 pl18a pl22a pl27a i/o af29 pl19d pl23d pl28d i/o ag31 pl19c pl23c pl28c i/o ag30 pl19b pl23b pl28b i/o ag29 pl19a pl23a pl28a i/o af28 pl20d pl24d pl29a i/o ah31 pl20c pl24c pl30c i/o ah30 pl20b pl24b pl30b i/o ah29 pl20a pl24a pl30a i/o-a15 ag28 cclk cclk cclk cclk pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout (continued) pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 118 lucent technologies inc. ah27 pb1a pb1a pb1a i/o-a16 aj28 pb1b pb1b pb1b i/o ak28 pb1c pb1c pb2a i/o al28 pb1d pb1d pb2d i/o ah26 pb2a pb2a pb3a i/o aj27 pb2b pb2b pb3b i/o ak27 pb2c pb2c pb3c i/o al27 pb2d pb2d pb3d i/o-v dd 5 aj26 pb3a pb3a pb4a i/o ak26 pb3b pb3b pb4b i/o al26 pb3c pb3c pb4c i/o ah24 pb3d pb3d pb4d i/o aj25 pb4a pb4a pb5a i/o ak25 pb4b pb4b pb5b i/o al25 pb4c pb4c pb5c i/o ah23 pb4d pb4d pb5d i/o-a17 aj24 pb5a pb5a pb6a i/o ak24 pb5b pb5b pb6b i/o aj23 pb5c pb5c pb6c i/o ah22 pb5d pb5d pb6d i/o ak23 pb6a pb6a pb7a i/o al23 pb6b pb6b pb7d i/o aj22 pb6c pb6c pb8a i/o ak22 pb6d pb6d pb8d i/o al22 pb7a pb7a pb9a i/o aj21 pb7b pb7b pb9d i/o ah20 pb7c pb7c pb10a i/o ak21 pb7d pb7d pb10d i/o al21 pb8a pb11a i/o-v dd 5 aj20 pb8a pb8b pb11b i/o ah19 pb8b pb8d pb11d i/o ak20 pb8c pb9a pb12a i/o aj19 pb9b pb12b i/o ak19 pb8d pb9d pb12d i/o ah18 pb9a pb10a pb13a i/o al19 pb9b pb10d pb13d i/o aj18 pb9c pb11a pb14a i/o ak18 pb11b pb14b i/o al18 pb9d pb11d pb14d i/o aj17 pb10a pb12a pb15a i/o ak17 pb10b pb12b pb15b i/o al17 pb10c pb12c pb15c i/o aj16 pb10d pb12d pb15d i/o ah16 pb11a pb13a pb16a i/o pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout (continued) pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 119 ak16 pb11b pb13b pb16b i/o al15 pb11c pb13c pb16c i/o ak15 pb11d pb13d pb16d i/o aj15 pb12a pb14a pb17a i/o-v dd 5 al14 pb12b pb14d pb17d i/o ak14 pb12c pb15a pb18a i/o aj14 pb15b pb18b i/o al13 pb12d pb15d pb18d i/o ah14 pb13a pb16a pb19a i/o-hdc ak13 pb16b pb19b i/o aj13 pb13b pb16d pb19d i/o ak12 pb13c pb17a pb20a i/o ah13 pb17b pb20b i/o aj12 pb13d pb17d pb20d i/o al11 pb14a pb18a pb21a i/o- ldc ak11 pb14b pb18b pb21d i/o ah12 pb14c pb18c pb22a i/o aj11 pb14d pb18d pb22d i/o al10 pb15a pb19a pb23a i/o ak10 pb15b pb19b pb24a i/o aj10 pb15c pb19c pb24c i/o al9 pb15d pb19d pb24d i/o ak9 pb16a pb20a pb25a i/o- init ah10 pb16b pb20b pb25b i/o aj9 pb16c pb20c pb25c i/o ak8 pb16d pb20d pb25d i/o aj8 pb17a pb21a pb26a i/o-v dd 5 ah9 pb17b pb21b pb26b i/o al7 pb17c pb21c pb26c i/o ak7 pb17d pb21d pb26d i/o aj7 pb18a pb22a pb27a i/o ah8 pb18b pb22b pb27b i/o al6 pb18c pb22c pb27c i/o ak6 pb18d pb22d pb27d i/o aj6 pb19a pb23a pb28a i/o al5 pb19b pb23b pb28b i/o ak5 pb19c pb23c pb28c i/o aj5 pb19d pb23d pb28d i/o ah6 pb20a pb24a pb29a i/o al4 pb20b pb24b pb29d i/o ak4 pb20c pb24c pb30c i/o aj4 pb20d pb24d pb30d i/o ah5 done done done done ag4 reset reset reset reset pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout (continued) pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 120 lucent technologies inc. ah3 prgm prgm prgm prgm ah2 pr20a pr24a pr30a i/o-m0 ah1 pr20b pr24b pr30b i/o af4 pr20c pr24c pr29a i/o ag3 pr20d pr24d pr29d i/o ag2 pr19a pr23a pr28a i/o-v dd 5 ag1 pr19b pr23b pr28b i/o af3 pr19c pr23c pr28c i/o af2 pr19d pr23d pr28d i/o af1 pr18a pr22a pr27a i/o ad4 pr18b pr22b pr27b i/o ae3 pr18c pr22c pr27c i/o ae2 pr18d pr22d pr27d i/o ae1 pr17a pr21a pr26a i/o ac4 pr17b pr21b pr26b i/o ad3 pr17c pr21c pr26c i/o ad2 pr17d pr21d pr25a i/o ac3 pr16a pr20a pr24a i/o ab4 pr16b pr20b pr24b i/o ac2 pr16c pr20c pr24d i/o ac1 pr16d pr20d pr23d i/o-m1 ab3 pr15a pr19a pr22a i/o ab2 pr15b pr19b pr22b i/o ab1 pr15c pr19c pr22c i/o aa3 pr15d pr19d pr22d i/o-v dd 5 y4 pr14a pr18a pr21a i/o aa2 pr14b pr18b pr21b i/o aa1 pr14c pr18c pr21c i/o y3 pr14d pr18d pr21d i/o w4 pr13a pr17a pr20a i/o-m2 y2 pr13b pr17d pr20d i/o w3 pr13c pr16a pr19a i/o w2 pr13d pr16b pr19b i/o v4 pr16d pr19d i/o w1 pr12a pr15a pr18a i/o-m3 v3 pr15d pr18d i/o v2 pr12b pr14a pr17a i/o v1 pr12c pr14b pr17b i/o u3 pr12d pr14d pr17d i/o u2 pr11a pr13a pr16a i/o u1 pr11b pr13b pr16b i/o t3 pr11c pr13c pr16c i/o t4 pr11d pr13d pr16d i/o t2 pr10a pr12a pr15a i/o pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout (continued) pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 121 r1 pr10b pr12b pr15b i/o r2 pr10c pr12c pr15c i/o r3 pr10d pr12d pr15d i/o p1 pr9a pr11a pr14a i/o-v dd 5 p2 pr9b pr11c pr14c i/o p3 pr9c pr11d pr14d i/o n1 pr10a pr13a i/o p4 pr9d pr10c pr13c i/o n2 pr10d pr13d i/o n3 pr8a pr9a pr12a i/o-cs1 m2 pr8b pr9d pr12d i/o n4 pr8c pr8a pr11a i/o m3 pr8d pr8d pr11d i/o l1 pr7a pr7a pr10a i/o- cs0 l2 pr7b pr7b pr10b i/o m4 pr7c pr7c pr10c i/o l3 pr7d pr7d pr10d i/o k1 pr6a pr6a pr9a i/o k2 pr6b pr6b pr9b i/o k3 pr6c pr6c pr9c i/o j1 pr6d pr6d pr9d i/o j2 pr5a pr5a pr8a i/o- rd k4 pr5b pr5b pr7a i/o j3 pr5c pr5c pr7c i/o h2 pr5d pr5d pr6a i/o h3 pr4a pr4a pr5a i/o-v dd 5 j4 pr4b pr4b pr5b i/o g1 pr4c pr4c pr5c i/o g2 pr4d pr4d pr5d i/o g3 pr3a pr3a pr4a i/o- wr h4 pr3b pr3b pr4b i/o f1 pr3c pr3c pr4c i/o f2 pr3d pr3d pr4d i/o f3 pr2a pr2a pr3a i/o e1 pr2b pr2b pr3b i/o e2 pr2c pr2c pr3c i/o e3 pr2d pr2d pr3d i/o f4 pr1a pr1a pr2a i/o d1 pr1b pr1b pr2d i/o d2 pr1c pr1c pr1a i/o d3 pr1d pr1d pr1d i/o e4 rd_cfgn rd_cfgn rd_cfgn rd_cfgn d5 pt20d pt24d pt30d i/o c4 pt20c pt24c pt30a i/o pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout (continued) pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 122 lucent technologies inc. b4 pt20b pt24b pt29b i/o a4 pt20a pt24a pt29a i/o d6 pt19d pt23d pt28d i/o c5 pt19c pt23c pt28c i/o b5 pt19b pt23b pt28b i/o a5 pt19a pt23a pt28a i/o-rdy/rclk c6 pt18d pt22d pt27d i/o b6 pt18c pt22c pt27c i/o a6 pt18b pt22b pt27b i/o d8 pt18a pt22a pt27a i/o c7 pt17d pt21d pt26d i/o b7 pt17c pt21c pt26c i/o a7 pt17b pt21b pt26b i/o d9 pt17a pt21a pt26a i/o c8 pt16d pt20d pt25d i/o-d7 b8 pt16c pt20c pt25c i/o c9 pt16b pt20b pt25b i/o d10 pt16a pt20a pt25a i/o b9 pt15d pt19d pt24d i/o-v dd 5 a9 pt15c pt19c pt24c i/o c10 pt15b pt19b pt24b i/o b10 pt15a pt19a pt23d i/o a10 pt14d pt18d pt22d i/o c11 pt14c pt18c pt22a i/o d12 pt14b pt18b pt21d i/o-d6 b11 pt14a pt18a pt21a i/o a11 pt13d pt17d pt20d i/o c12 pt13c pt17a pt20a i/o d13 pt16d pt19d i/o-v dd 5 b12 pt13b pt16b pt19b i/o c13 pt13a pt16a pt19a i/o-d5 b13 pt12d pt15d pt18d i/o d14 pt15b pt18b i/o a13 pt12c pt15a pt18a i/o c14 pt12b pt14d pt17d i/o b14 pt14b pt17b i/o a14 pt12a pt14a pt17a i/o-d4 c15 pt11d pt13d pt16d i/o b15 pt11c pt13c pt16c i/o a15 pt11b pt13b pt16b i/o c16 pt11a pt13a pt16a i/o-d3 d16 pt10d pt12d pt15d i/o b16 pt10c pt12c pt15c i/o a17 pt10b pt12b pt15b i/o-v dd 5 pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout (continued) pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 123 b17 pt10a pt12a pt15a i/o-d2 c17 pt9d pt11d pt14d d1 a18 pt11c pt14c i/o b18 pt9c pt11a pt14a i/o c18 pt9b pt10d pt13d i/o a19 pt10c pt13c i/o d18 pt9a pt10a pt13a i/o-d0/din b19 pt8d pt9d pt12d i/o c19 pt9c pt12c i/o b20 pt8c pt9a pt12a i/o d19 pt8b pt8d pt11d i/o c20 pt8a pt8a pt11a i/o-dout a21 pt7d pt7d pt10d i/o b21 pt7c pt7c pt10a i/o d20 pt7b pt7b pt9d i/o c21 pt7a pt7a pt9a i/o a22 pt6d pt6d pt8d i/o b22 pt6c pt6c pt8a i/o c22 pt6b pt6b pt7d i/o a23 pt6a pt6a pt7a i/o-tdi b23 pt5d pt5d pt6d i/o d22 pt5c pt5c pt6c i/o c23 pt5b pt5b pt6b i/o b24 pt5a pt5a pt6a i/o-v dd 5 c24 pt4d pt4d pt5d i/o d23 pt4c pt4c pt5c i/o a25 pt4b pt4b pt5b i/o b25 pt4a pt4a pt5a i/o-tms c25 pt3d pt3d pt4d i/o d24 pt3c pt3c pt4c i/o a26 pt3b pt3b pt4b i/o b26 pt3a pt3a pt4a i/o c26 pt2d pt2d pt3d i/o a27 pt2c pt2c pt3c i/o b27 pt2b pt2b pt3b i/o c27 pt2a pt2a pt3a i/o d26 pt1d pt1d pt2d i/o a28 pt1c pt1c pt2a i/o b28 pt1b pt1b pt1d i/o c28 pt1a pt1a pt1a i/o-tck d27 rd_data/tdo rd_data/tdo rd_data/tdo rd_data/tdo a12 v ss v ss v ss v ss a16 v ss v ss v ss v ss a2 v ss v ss v ss v ss pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout (continued) pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet orca series 2 fpgas june 1999 124 lucent technologies inc. a20 v ss v ss v ss v ss a24 v ss v ss v ss v ss a29 v ss v ss v ss v ss a3 v ss v ss v ss v ss a30 v ss v ss v ss v ss a8 v ss v ss v ss v ss ad1 v ss v ss v ss v ss ad31 v ss v ss v ss v ss aj1 v ss v ss v ss v ss aj2 v ss v ss v ss v ss aj30 v ss v ss v ss v ss aj31 v ss v ss v ss v ss ak1 v ss v ss v ss v ss ak29 v ss v ss v ss v ss ak3 v ss v ss v ss v ss ak31 v ss v ss v ss v ss al12 v ss v ss v ss v ss al16 v ss v ss v ss v ss al2 v ss v ss v ss v ss al20 v ss v ss v ss v ss al24 v ss v ss v ss v ss al29 v ss v ss v ss v ss al3 v ss v ss v ss v ss al30 v ss v ss v ss v ss al8 v ss v ss v ss v ss b1 v ss v ss v ss v ss b29 v ss v ss v ss v ss b3 v ss v ss v ss v ss b31 v ss v ss v ss v ss c1 v ss v ss v ss v ss c2 v ss v ss v ss v ss c30 v ss v ss v ss v ss c31 v ss v ss v ss v ss h1 v ss v ss v ss v ss h31 v ss v ss v ss v ss m1 v ss v ss v ss v ss m31 v ss v ss v ss v ss t1 v ss v ss v ss v ss t31 v ss v ss v ss v ss y1 v ss v ss v ss v ss y31 v ss v ss v ss v ss a1 v dd v dd v dd v dd a31 v dd v dd v dd v dd pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout (continued) pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 125 aa28 v dd v dd v dd v dd aa4 v dd v dd v dd v dd ae28 v dd v dd v dd v dd ae4 v dd v dd v dd v dd ah11 v dd v dd v dd v dd ah15 v dd v dd v dd v dd ah17 v dd v dd v dd v dd ah21 v dd v dd v dd v dd ah25 v dd v dd v dd v dd ah28 v dd v dd v dd v dd ah4 v dd v dd v dd v dd ah7 v dd v dd v dd v dd aj29 v dd v dd v dd v dd aj3 v dd v dd v dd v dd ak2 v dd v dd v dd v dd ak30 v dd v dd v dd v dd al1 v dd v dd v dd v dd al31 v dd v dd v dd v dd b2 v dd v dd v dd v dd b30 v dd v dd v dd v dd c29 v dd v dd v dd v dd c3 v dd v dd v dd v dd d11 v dd v dd v dd v dd d15 v dd v dd v dd v dd d17 v dd v dd v dd v dd d21 v dd v dd v dd v dd d25 v dd v dd v dd v dd d28 v dd v dd v dd v dd d4 v dd v dd v dd v dd d7 v dd v dd v dd v dd g28 v dd v dd v dd v dd g4 v dd v dd v dd v dd l28 v dd v dd v dd v dd l4 v dd v dd v dd v dd r28 v dd v dd v dd v dd r4 v dd v dd v dd v dd u28 v dd v dd v dd v dd u4 v dd v dd v dd v dd pin information (continued) table 28. or2c/2t15a, or2c/2t26a, and or2c/2t40a/b 432-pin ebga pinout (continued) pin 2c/2t15a pad 2c/2t26a pad 2c/2t40a/b pad function notes: the or2t15a pin ag2 is not connected in the 432-pin ebga package. the pins labeled i/o-v dd 5 are user i/os for the or2cxxa and or2txxb series, but they are connected to v dd 5 for the or2txxa series.
lucent technologies inc. 126 data sheet june 1999 orca series 2 fpgas package thermal characteristics there are three thermal parameters that are in com- mon use: q ja , y jc, and q jc . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. the data base containing the thermal values for all of lucent technologies ic packages is currently being updated to conform to modern jedec standards. thus, table 29 contains the currently available thermal specifications for lucent technologies fpga pack- ages mounted on both jedec and non-jedec test boards. the thermal values for the newer package types correspond to those packages mounted on a jedec four-layer board (indicated as note 2 in the table). the values for the older packages, however, cor- respond to those packages mounted on a non-jedec, single-layer, sparse copper board (see note 1). it should also be noted that the values for the older pack- ages are considered conservative. q ja this is the thermal resistance from junction to ambient (a.k.a. theta-ja, r-theta, etc.). where t j is the junction temperature, t a is the ambient air temperature, and q is the chip power. experimentally, q ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced convection measurements. a controlled amount of power (q) is dissipated in the test chips heater resistor, the chips temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that q ja is expressed in units of c/watt. y jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance, and it is defined by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the q ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. y jc is also expressed in units of c/watt. q jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is defined by: the parameters in this equation have been defined above. however, the measurements is performed with the case of the part pressed against a water-cooled heat sink so as to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates q jc from y jc. q jc is a true thermal resistance and is expressed in units of c/watt. q jb this is the thermal resistance from junction to board (a.k.a., q jl) . it is defined by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been defined above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board so as to draw most of the heat out of the leads. note that q jb is expressed in units of c/watt, and that this parameter and the way it is measured is still in jedec committee. q ja t j t a C q ------------------- - = y jc t j t c C q -------------------- = q jc t j t c C q -------------------- = q jb t j t b C q ------------------- - =
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 127 package thermal characteristics (continued) fpga maximum junction temperature once the power dissipated by the fpga has been determined (see the estimating power dissipation section), the maximum junction temperature of the fpga can be found. this is needed to determine if speed derating of the device from the 85 c junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in c), the maximum junction tempera- ture is approximated by: t jmax = t amax + (q ? q ja ) table 29 lists the thermal characteristics for all packages used with the series 2 fpgas. 1. mounted on a sparse copper one-layer test board. 2. mounted on four-layer jedec standard test board with two power/ground planes. 3. with thermal balls connected to board ground plane. 4. without thermal balls connected to board ground plane. note: the y jc for the packages listed is <1 c/w. this implies that virtually all of the heat is dissipated through the board on which the pa ckage is mounted. table 29. series 2 plastic package thermal guidelines package q ja (c/w) t a = 70 c max t j = 125 c max @ 0 fpm (w) 0 fpm 200 fpm 500 fpm 84-pin plcc 1 40.0 35.0 1.4 100-pin tqfp 2 30.027.0 2623 24.021.0 1.82.0 144-pin tqfp 1 52.0 39.0 1.1 160-pin qfp 2 24.0 21.5 20.5 2.3 208-pin sqfp 2 26.5 23.0 21.0 2.1 208-pin sqfp2 2 12.8 10.3 9.1 4.3 240-pin sqfp 2 25.5 22.5 21.0 2.2 240-pin sqfp2 2 13.0 10.0 9.0 4.2 256-pin pbga 2, 3 22.5 19.0 17.5 2.4 256-pin pbga 2, 4 26.0 22.0 20.5 2.1 304-pin sqfp 2 27.5 24.0 22.5 2.0 304-pin sqfp2 2 12.0 10.0 9.0 4.6 352-pin pbga 2, 3 19.0 16.0 15.0 2.9 352-pin pbga 2, 4 25.5 22.0 20.5 2.1 432-pin ebga 2 11.0 8.5 7.5 5.0 package coplanarity the coplanarity limits of the series 2 series packages are as follows: n tqfp: 3.15 mils n plcc and qfp: 4.0 mils n pbga: 8.0 mils n sqfp: 4.0 mils (240 and 304 only) 3.15 mils (all other sizes) n sqfp2: 3.15 mils n ebga: 8.0 mils package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 30 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead.
data sheet orca series 2 fpgas june 1999 128 lucent technologies inc. package parasitics (continued) these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capaci- tances in pf are listed: c m , the mutual capacitance of the lead to the nearest neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. the parasitic values in table 30 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designers model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. 5-3862(f).r2 figure 53. package parasitics table 30. series 2 package parasitics package type l sw l mw r w c 1 c 2 c m l sl l ml 84-pin plcc 3 1 140 1 1 0.5 711 36 100-pin tqfp 3 1 150 0.5 0.5 0.4 46 23 144-pin tqfp 3 1 140 1 1 0.6 46 22.5 160-pin qfp 4 1.5 180 1.5 1.5 1 1013 68 208-pin sqfp 4 2 200 1 1 1 710 46 208-pin sqfp2 4 2 200 1 1 1 69 46 240-pin sqfp 4 2 200 1 1 1 812 58 240-pin sqfp2 4 2 200 1 1 1 711 47 256-pin pbga 5 2 220 1 1 1 58 24 304-pin sqfp 5 2 220 1 1 1 1218 712 304-pin sqfp2 5 2 220 1 1 1 1117 712 352-pin pbga 5 2 220 1.5 1.5 1.5 712 36 432-pin ebga 4 1.5 500 1 1 0.3 35.5 0.51 pad n circuit board pad c m c 1 l w r w l l l mw c 2 c 1 l ml c 2 pad n + 1 l w r w l l
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 129 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series fpgas include circuitry designed to protect the chips from damaging substrate injection currents and prevent accumulations of static charge. nevertheless, conventional precautions should be observed during stor- age, handling, and use to avoid exposure to excessive electrical stress. recommended operating conditions notes: during powerup and powerdown sequencing, v dd is allowed to be at a higher voltage level than v dd 5 for up to 100 ms. during powerup sequencing of or2txxa devices v dd should reach 1.0 v before voltage applied to v dd 5 can be greater than the voltage applied to v dd. the maximum recommended junction temperature (t j ) during operation is 125 c. * v dd 5 not used in or2txxb devices. parameter symbol min max unit storage temperature t stg C65 150 c supply voltage with respect to ground v dd C0.5 7.0 v v dd 5 supply voltage with respect to ground (or2txxa) v dd 5v dd 7.0 v input signal with respect to ground or2txxa only C0.5 v dd + 0.3 v dd 5 + 0.3 v signal applied to high-impedance output or2txxa only C0.5 v dd + 0.3 v dd 5 + 0.3 v maximum soldering temperature 260 c mode or2cxxa or2txxa/or2txxb temperature range (ambient) supply voltage (v dd ) temperature range (ambient) supply voltage (v dd ) supply voltage* (v dd 5) commercial 0 c to 70 c 5 v 5% 0 c to 70 c 3.0 v to 3.6 v v dd to 5.25 v industrial C40 c to +85 c 5 v 10% C40 c to +85 c 3.0 v to 3.6 v v dd to 5.25 v
data sheet orca series 2 fpgas june 1999 130 lucent technologies inc. electrical characteristics * on the or2txxa devices, the pull-up resistor will externally pull the pin to a level 1.0 v below v dd . table 31a. or2cxxa and or2txxa electrical characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter sym- bol test conditions or2cxxa or2txxa unit min max min max input voltage: high low v ih v il input configured as cmos 50% v dd gnd C 0.5 v dd + 0.3 30% v dd 50% v dd5 gnd C 0.5 v dd5 + 0.3 30% v dd5 v v input voltage: high low v ih v il input configured as ttl (valid for or2cxxa only) 2.0 C0.5 v dd + 0.3 0.8 v v output voltage: high low v oh v ol v dd = min, i oh = 6 ma or 3 ma v dd = min, i ol = 12 ma or 6 ma 2.4 0.4 2.4 0.4 v v input leakage current i l v dd = max, v in = v ss or v dd C10 10 C10 10 a standby current: or2c04a/or2t04a or2c06a/or2t06a or2c08a/or2t08a or2c10a/or2t10a or2c12a/or2t12a or2c15a/or2t15a or2c26a/or2t26a or2c40a/or2t40a i ddsb or2cxxa (t a = 25 c, v dd = 5.0 v) or2txxa (t a = 25 c, v dd = 3.3 v) internal oscillator running, no output loads, inputs at v dd or gnd (after configuration) 6.5 7.0 7.7 8.4 9.2 10.0 12.2 16.3 4.0 4.3 4.8 5.3 5.8 6.3 7.8 10.6 ma ma ma ma ma ma ma ma standby current: or2c04a/or2t04a or2c06a/or2t06a or2c08a/or2t08a or2c10a/or2t10a or2c12a/or2t12a or2c15a/or2t15a or2c26a/or2t26a or2c40a/or2t40a i ddsb or2cxxa (t a = 25 c, v dd = 5.0 v) or2txxa (t a = 25 c, v dd = 3.3 v) internal oscillator stopped, no output loads, inputs at v dd or gnd (after configuration) 1.5 2.0 2.7 3.4 4.2 5.0 7.2 11.3 1.0 1.3 1.8 2.3 2.8 3.3 4.8 7.6 ma ma ma ma ma ma ma ma data retention voltage v dr t a = 25 c 2.3 2.3 v input capacitance c in or2cxxa (t a = 25 c, v dd = 5.0 v) or2txxa (t a = 25 c, v dd = 3.3 v) test frequency = 1 mhz 9 9pf output capacitance c out or2cxxa (t a = 25 c, v dd = 5.0 v) or2txxa (t a = 25 c, v dd = 3.3 v) test frequency = 1 mhz 9 9pf done pull-up resistor* r done 100k 100k w m3, m2, m1, and m0 pull-up resistors* r m 100k 100k w i/o pad static pull-up current* i pu or2cxxa (v dd = 5.25 v, v in = v ss , t a = 0 c) or2txxa (v dd = 3.6 v, v in = v ss , t a = 0 c) 14.4 50.9 14.4 50.9 a i/o pad static pull-down current i pd or2cxxa (v dd = 5.25 v, v in = v ss , t a = 0 c) or2txxa (v dd = 3.6 v, v in = v ss , t a = 0 c) 26 103 26 103 a i/o pad pull-up resistor* r pu v dd = all, v in = v ss , t a = 0 c 100k 100k w i/o pad pull-down resistor r pd v dd = all, v in = v dd , t a = 0 c 50k 50k w
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 131 electrical characteristics (continued) * on the or2txxb devices, the pull-up resistor will externally pull the pin to a level 1.0 v below v dd . table 31b. or2txxb electrical characteristics or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol test conditions or2txxb unit min max input voltage: high low v ih v il input configured as cmos 80% v dd gnd C 0.5 v dd + 0.3 15% v dd v v output voltage: high low v oh v ol v dd = min, i oh = 6 ma or 3 ma v dd = min, i ol = 12 ma or 6 ma 2.4 0.4 v v input leakage current i l v dd = max, v in = v ss or v dd C10 10 a standby current: or2t15b or2t40b i ddsb or2txxb (t a = 25 c, v dd = 3.3 v) internal oscillator running, no output loads, inputs at v dd or gnd (after configuration) 5.5 8.0 ma ma standby current: or2t15b or2t40b i ddsb or2txxb (t a = 25 c, v dd = 3.3 v) internal oscillator stopped, no output loads, inputs at v dd or gnd (after configuration) 2.0 4.5 ma ma data retention voltage v dr t a = 25 c 2.3 v input capacitance c in or2txxb (t a = 25 c, v dd = 3.3 v) test frequency = 1 mhz 8pf output capacitance c out or2txxb (t a = 25 c, v dd = 3.3 v) test frequency = 1 mhz 8pf done pull-up resistor* r done 100k w m3, m2, m1, and m0 pull-up resistors* r m 100k w i/o pad static pull-up current* i pu v dd = 3.6 v, v in = v ss , t a = 0 c 14.4 50.9 a i/o pad static pull-down cur- rent i pd v dd = 3.6 v, v in = v dd , t a = 0 c 26 103 a i/o pad pull-up resistor* r pu v dd = all, v in = v ss , t a = 0 c 100k w i/o pad pull-down resistor r pd v dd = all, v in = v dd , t a = 0 c 50k w
data sheet orca series 2 fpgas june 1999 132 lucent technologies inc. timing characteristics note: speed grades of -5, -6, and -7 are for or2txxa devices only. table 32a. or2cxxa and or2txxa combinatorial pfu timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max combinatorial delays (t j = +85 c, v dd = min): four input variables (a[4:0], b[4:0] to f[3:0]) five input variables (a[4:0], b[4:0] to f3, f0) pfumux (a[4:0], b[4:0] to f1) pfumux (c0 to f1) pfunand (a[4:0], b[4:0] to f2) pfunand (c0 to f2) pfuxor (a[4:0], b[4:0] to f1) pfuxor (c0 to f1) f4*_del f5*_del mux_del c0mux_del nd_del c0nd_del xor_del c0xor_del 4.0 4.1 4.7 3.0 4.7 2.7 5.6 3.1 2.8 2.9 3.8 2.2 4.0 2.2 4.5 2.2 2.1 2.2 3.2 1.9 3.3 1.8 3.8 2.0 1.7 1.8 2.6 1.5 2.7 1.5 3.1 1.6 1.4 1.4 1.9 1.1 1.8 1.0 2.3 1.1 1.3 1.3 1.8 1.0 1.7 0.8 2.1 1.0 ns ns ns ns ns ns ns ns table 32b. or2txxb combinatorial pfu timing characteristics or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max combinatorial delays (t j = +85 c, v dd = min): four input variables (a[4:0], b[4:0] to f[3:0]) five input variables (a[4:0], b[4:0] to f3, f0) pfumux (a[4:0], b[4:0] to f1) pfumux (c0 to f1) pfunand (a[4:0], b[4:0] to f2) pfunand (c0 to f2) pfuxor (a[4:0], b[4:0] to f1) pfuxor (c0 to f1) f4*_del f5*_del mux_del c0mux_del nd_del c0nd_del xor_del c0xor_del 1.3 1.3 2.2 1.4 2.1 1.2 2.5 1.3 1.0 1.0 1.8 1.0 1.7 0.9 2.0 1.0 ns ns ns ns ns ns ns ns
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 133 timing characteristics (continued) 5-4633(f).a c = controlled by configuration ram. notes: the parameters mux_del, xor_del, and nd_del include the delay through the lut in f5a/f5b modes. see table 41 for an explanation of fdbk_del and omux_del. figure 54. combinatorial pfu timing a[4:0], b[4:0] a[4:0], b[4:0] a[4:0], b[4:0] f4*_del (lut) pfu 4 f5*_del (lut) 2 (lut) 2 c0 mux_del c f[3:0] f3, f0 f1 f2 o[4:0] fdbk_del xsw lines output mux omux_del c0mux_del, c0xor_del, c0nd_del xor_del nd_del
data sheet orca series 2 fpgas june 1999 134 lucent technologies inc. timing characteristics (continued) 1.the input buffers contain a programmable delay to allow the hold time vs. the external clock pin to be equal to 0. note: speed grades of -5, -6, and -7 are for or2txxa devices only. table 33a. or2cxxa and or2txxa sequential pfu timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max input requirements clock low time t cl 3.2 2.5 2.0 1.8 1.7 1.6 ns clock high time t ch 3.2 2.5 2.0 1.8 1.7 1.6 ns global s/r pulse width (gsrn) t rw 2.8 2.5 2.0 1.8 1.7 1.6 ns local s/r pulse width t pw 3.0 2.5 2.0 1.8 1.7 1.6 ns combinatorial setup times (t j = 85 c, v dd = min): four input variables to clock (a[4:0], b[4:0] to ck) five input variables to clock (a[4:0], b[4:0] to ck) pfumux to clock (a[4:0], b[4:0] to ck) pfumux to clock (c0 to ck) pfunand to clock (a[4:0], b[4:0] to ck) pfunand to clock (c0 to ck) pfuxor to clock (a[4:0], b[4:0] to ck) pfuxor to clock (c0 to ck) data in to clock (wd[3:0] to ck) clock enable to clock (ce to ck) local set/reset (synchronous) (lsr to ck) data select to clock (sel to ck) pad direct in f4*_set f5*_set mux_set c0mux_set nd_set c0nd_set xor_set c0xor_set d*_set cken_set lsr_set select_set pdin_set 2.4 2.5 3.9 1.5 3.9 1.7 4.8 1.6 0.5 1.6 1.7 1.9 0.0 1.7 1.9 2.9 1.2 2.9 1.2 3.6 1.2 0.1 1.2 1.4 1.5 0.0 1.3 1.3 2.3 0.9 2.2 0.6 3.0 0.9 0.1 1.0 1.3 1.4 0.0 1.1 1.2 2.1 0.8 2.0 0.5 2.7 0.8 0.0 0.9 1.2 1.3 0.0 1.0 1.0 1.6 0.7 1.7 0.5 2.1 0.7 0.1 0.9 1.1 1.2 0.0 0.9 0.9 1.5 0.6 1.6 0.5 2.0 0.6 0.1 0.6 0.8 1.0 0.0 ns ns ns ns ns ns ns ns ns ns ns ns ns combinatorial hold times (t j = all, v dd = all): data in (wd[3:0] from ck) clock enable (ce from ck) local set/reset (synchronous) (lsr from ck) data select (sel from ck) pad direct in hold (dia[3:0], dib[3:0] to ck) 1 all others d*_hld cken_hld lsr_hld select_hld pdin_hld 0.6 0.6 0.0 0.0 1.5 0.0 0.4 0.4 0.0 0.0 1.4 0.0 0.4 0.0 0.0 0.0 1.0 0.0 0.4 0.0 0.0 0.0 0.9 0.0 0.3 0.0 0.0 0.0 0.8 0.0 0.3 0.0 0.0 0.0 0.8 0.0 ns ns ns ns ns ns output characteristics sequential delays (t j = 85 c, v dd = min): local s/r (async) to pfu out (lsr to q[3:0]) global s/r to pfu out (gsrn to q[3:0]) clock to pfu out (ck to q[3:0])register clock to pfu out (ck to q[3:0])latch transparent latch (wd[3:0] to q[3:0]) lsr_del gsr_del reg_del ltch_del ltch_ddel 4.5 2.9 2.4 2.5 3.5 3.4 2.3 2.0 2.0 2.7 3.1 2.0 1.9 1.9 2.5 2.5 1.6 1.5 1.5 2.0 2.0 1.3 1.3 1.3 2.0 1.6 1.2 1.0 1.0 1.8 ns ns ns ns ns
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 135 timing characteristics (continued) 1.the input buffers contain a programmable delay to allow the hold time vs. the external clock pin to be equal to 0. table 33b. or2txxb sequential pfu timing characteristics or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max input requirements clock low time t cl 1.7 1.4 ns clock high time t ch 1.7 1.4 ns global s/r pulse width (gsrn) t rw 1.7 1.4 ns local s/r pulse width t pw 1.7 1.4 ns combinatorial setup times (t j = 85 c, v dd = min): four input variables to clock (a[4:0], b[4:0] to ck) five input variables to clock (a[4:0], b[4:0] to ck) pfumux to clock (a[4:0], b[4:0] to ck) pfumux to clock (c0 to ck) pfunand to clock (a[4:0], b[4:0] to ck) pfunand to clock (c0 to ck) pfuxor to clock (a[4:0], b[4:0] to ck) pfuxor to clock (c0 to ck) data in to clock (wd[3:0] to ck) clock enable to clock (ce to ck) local set/reset (synchronous) (lsr to ck) data select to clock (sel to ck) pad direct in f4*_set f5*_set mux_set c0mux_set nd_set c0nd_set xor_set c0xor_set d*_set cken_set lsr_set select_set pdin_set 1.0 1.0 1.3 1.1 1.0 0.8 1.3 1.1 0.2 1.0 1.0 1.0 0.0 0.8 0.8 1.3 0.8 0.8 0.7 1.3 0.8 0.1 0.8 0.8 0.8 0.0 ns ns ns ns ns ns ns ns ns ns ns ns ns combinatorial hold times (t j = all, v dd = all): data in (wd[3:0] from ck) clock enable (ce from ck) local set/reset (synchronous) (lsr from ck) data select (sel from ck) pad direct in hold (dia[3:0], dib[3:0] to ck) 1 all others d*_hld cken_hld lsr_hld select_hld pdin_hld 0.0 0.0 0.0 0.0 0.1 0.0 0.0 0.0 0.0 0.0 0.1 0.0 ns ns ns ns ns ns output characteristics sequential delays (t j = 85 c, v dd = min): local s/r (async) to pfu out (lsr to q[3:0]) global s/r to pfu out (gsrn to q[3:0]) clock to pfu out (ck to q[3:0])register clock to pfu out (ck to q[3:0])latch transparent latch (wd[3:0] to q[3:0]) lsr_del gsr_del reg_del ltch_del ltch_ddel 2.2 1.4 1.0 1.0 1.7 1.8 1.0 1.0 1.0 1.4 ns ns ns ns ns
data sheet orca series 2 fpgas june 1999 136 lucent technologies inc. timing characteristics (continued) table 34a. or2cxxa and or2txxa ripple mode pfu timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max ripple setup times (t j = +85 c, v dd = min): operands to clock (a[3:0], b[3:0] to ck) bitwise operands to clock (a[i], b[i] to ck at f[i]) carry-in from fast carry to clock (cin to ck) carry-in from general routing to clock (b4 to ck) add/subtract to clock (a4 to ck) rip_set frip_set cin_set b4_set as_set 6.7 2.4 4.0 4.0 8.2 5.0 1.7 3.2 3.2 5.6 3.7 1.3 1.9 1.9 4.3 3.3 1.2 1.7 1.7 3.9 2.8 1.0 1.4 1.4 3.2 2.5 0.9 1.3 1.3 3.1 ns ns ns ns ns ripple hold times (t j = all, v dd = all): all th 0.0 0.0 0.0 0.0 0.0 0.0 ns ripple delays (t j = 85 c, v dd = min): operands to carry-out (a[3:0], b[3:0] to cout) operands to carry-out (a[3:0], b[3:0] to o4) operands to pfu out (a[3:0], b[3:0] to f[3:0]) bitwise operands to pfu out (a[i], b[i] to f[i]) carry-in from fast carry to carry-out (cin to cout) carry-in from fast carry to carry-out (cin to o4) carry-in from fast carry to pfu out (cin to f[3:0]) carry-in from general routing to carry- out (b4 to cout) carry-in from general routing to carry- out (b4 to o4) carry-in from general routing to pfu out (b4 to f[3:0]) add/subtract to carry-out (a4 to cout) add/subtract to carry-out (a4 to o4) add/subtract to pfu out (a4 to f[3:0]) rip_codel rip_o4del rip_del frip_del cin_codel cin_o4del cin_del b4_codel b4_o4del b4_del as_codel as_o4del as_del 5.4 6.9 8.2 4.0 1.9 3.5 5.6 1.9 3.5 5.6 6.1 7.6 9.7 3.8 4.8 6.0 2.8 1.6 2.6 4.2 1.6 2.6 4.2 4.5 5.6 6.8 3.3 4.2 4.7 2.1 1.1 2.1 2.9 1.1 2.1 2.9 3.9 4.9 5.3 2.6 3.4 3.8 1.7 0.9 1.7 2.3 0.9 1.7 2.3 3.1 3.9 4.3 2.1 2.6 3.2 1.6 0.7 1.3 2.2 0.7 1.3 2.2 2.5 3.1 3.5 1.8 2.4 2.8 1.5 0.6 1.1 1.7 0.6 1.1 2.1 2.3 2.8 3.1 ns ns ns ns ns ns ns ns ns ns ns ns ns notes: the new 4 x 1 multiplier and 4-bit comparator submodes use the appropriate ripple mode timing shown above. speed grades of -5, -6, and -7 are for or2txxa devices only.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 137 timing characteristics (continued) table 34b. or2txxb ripple mode pfu timing characteristics or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max ripple setup times (t j = 85 c, v dd = min): operands to clock (a[3:0], b[3:0] to ck) bitwise operands to clock (a[i], b[i] to ck at f[i]) carry-in from fast carry to clock (cin to ck) carry-in from general routing to clock (b4 to ck) add/subtract to clock (a4 to ck) rip_set frip_set cin_set b4_set as_set 2.4 1.1 1.6 1.0 2.9 1.9 0.9 1.3 0.8 2.3 ns ns ns ns ns ripple hold times (t j = all, v dd = all): all th ns ripple delays (t j = 85 c, v dd = min): operands to carry-out (a[3:0], b[3:0] to cout) operands to carry-out (a[3:0], b[3:0] to o4) operands to pfu out (a[3:0], b[3:0] to f[3:0]) bitwise operands to pfu out (a[i], b[i] to f[i]) carry-in from fast carry to carry-out (cin to cout) carry-in from fast carry to carry-out (cin to o4) carry-in from fast carry to pfu out (cin to f[3:0]) carry-in from general routing to carry- out (b4 to cout) carry-in from general routing to carry- out (b4 to o4) carry-in from general routing to pfu out (b4 to f[3:0]) add/subtract to carry-out (a4 to cout) add/subtract to carry-out (a4 to o4) add/subtract to pfu out (a4 to f[3:0]) rip_codel rip_o4del rip_del frip_del cin_codel cin_o4del cin_del b4_codel b4_o4del b4_del as_codel as_o4del as_del 2.2 3.0 3.1 1.4 0.7 1.4 1.9 0.7 1.4 1.9 2.7 3.4 3.6 1.8 2.4 2.5 1.1 0.6 1.2 1.5 0.6 1.2 1.5 2.2 2.8 2.9 ns ns ns ns ns ns ns ns ns ns ns ns ns notes: the new 4 x 1 multiplier and 4-bit comparator submodes use the appropriate ripple mode timing shown above.
data sheet orca series 2 fpgas june 1999 138 lucent technologies inc. timing characteristics (continued) note: speed grades of -5, -6, and -7 are for or2txxa devices only. 5-3226(f).r4 figure 55. read operationflip-flop bypass 5-3227(f).r4 figure 56. read operationlut memory loading flip-flops table 35a. or2cxxa and or2txxa asynchronous memory read characteristics (ma/mb modes) or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max read operation (t j = 85 c, v dd = min): read cycle time data valid after address (a[3:0], b[3:0] to f[3:0]) t rc mem*_adel 5.1 4.0 3.6 2.8 2.7 2.1 2.4 1.7 2.3 1.4 2.0 1.3 ns ns read operation, clocking data into latch/flip-flop (t j = 85 c, v dd = min): address to clock setup time (a[3:0], b[3:0] to ck) clock to pfu out (ck to q[3:0])register mem*_aset reg_del 2.4 2.4 1.8 2.0 1.2 1.9 1.1 1.5 1.0 1.3 1.0 1.0 ns ns table 35b. or2txxb asynchronous memory read characteristics (ma/mb modes) or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max read operation (t j = 85 c, v dd = min): read cycle time data valid after address (a[3:0], b[3:0] to f[3:0]) t rc mem*_adel 1.9 1.3 1.8 1.0 ns ns read operation, clocking data into latch/flip-flop (t j = 85 c, v dd = min): address to clock setup time (a[3:0], b[3:0] to ck) clock to pfu out (ck to q[3:0])register mem*_aset reg_del 0.9 1.0 0.8 1.0 ns ns a[3:0], b[3:0] f[3:0] mem*_adel t rc a[3:0], b[3:0] ck mem*_aset reg_del q[3:0]
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 139 timing characteristics (continued) note: speed grades of -5, -6, and -7 are for or2txxa devices only. table 36a. or2cxxa and or2txxa asynchronous memory write characteristics (ma/mb modes) or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max write operation (tj = 85 c, vdd = min): write cycle time write enable (wren) pulse width (a4/b4) twc tpw 9.3 3.0 7.8 2.5 6.3 2.0 5.7 1.8 5.2 1.7 5.1 1.6 ns ns setup time (tj = 85 c, vdd = min): address to wren (a[3:0]/b[3:0] to a4/b4) data to wren (wd[3:0] to a4/b4) address to wpe (a[3:0]/b[3:0] to c0) data to wpe (wd[3:0] to c0) wpe to wren (c0 to a4/b4) mem*_awrset mem*_dwrset mem*_apwrset mem*_dpwrset mem*_wpeset 0.1 0.0 0.0 0.0 2.5 0.1 0.0 0.0 0.0 2.0 0.0 0.0 0.0 0.0 1.5 0.0 0.0 0.0 0.0 1.4 0.0 0.0 0.0 0.0 1.1 0.0 0.0 0.0 0.0 1.1 ns ns ns ns ns hold time (tj = all, vdd = all): address from wren (a[3:0]/b[3:0] from a4/b4) data from wren (wd[3:0] from a4/b4) address from wpe (a[3:0/b[3:0] to c0) data from wpe (wd[3:0] to c0) wpe from wren (c0 from a4/b4) mem*_wrahld mem*_wrdhld mem*_pwrahld mem*_pwrdhld mem*_wpehld 2.4 2.4 3.8 3.9 0.0 1.7 2.0 3.3 3.4 0.0 1.8 1.9 2.8 2.9 0.0 1.6 1.5 2.5 2.6 0.0 1.6 1.6 2.4 2.4 0.0 1.5 1.6 2.3 2.3 0.0 ns ns ns ns ns table 36b. or2txxb asynchronous memory write characteristics (ma/mb modes) or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 minmaxminmax write operation (t j = 85 c, v dd = min): write cycle time write enable (wren) pulse width (a4/b4) t wc t pw 5.1 1.7 4.2 1.4 ns ns setup time (t j = 85 c, v dd = min): address to wren (a[3:0]/b[3:0] to a4/b4) data to wren (wd[3:0] to a4/b4) address to wpe (a[3:0]/b[3:0] to c0) data to wpe (wd[3:0] to c0) wpe to wren (c0 to a4/b4) mem*_awrset mem*_dwrset mem*_apwrset mem*_dpwrset mem*_wpeset 0.0 0.0 0.0 0.0 1.0 0.0 0.0 0.0 0.0 0.8 ns ns ns ns ns hold time (t j = all, v dd = all): address from wren (a[3:0]/b[3:0] from a4/b4) data from wren (wd[3:0] from a4/b4) address from wpe (a[3:0/b[3:0] to c0) data from wpe (wd[3:0] to c0) wpe from wren (c0 from a4/b4) mem*_wrahld mem*_wrdhld mem*_pwrahld mem*_pwrdhld mem*_wpehld 0.9 1.6 2.3 2.3 0.0 0.7 1.3 1.9 1.9 0.0 ns ns ns ns ns
data sheet orca series 2 fpgas june 1999 140 lucent technologies inc. timing characteristics (continued) 5-3228(f).r6 figure 57. write operation a[3:0], b[3:0] wd[3:0] mem*_apwrset t wc c0 (wpe) mem*_pwrahld mem*_wpehld t pw mem*_wpeset a4, b4 (wren) mem*_wrahld mem*_pwrdhld mem*_dpwrset mem*_awrset mem*_dwrset mem*_wrdhld
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 141 timing characteristics (continued) note: speed grades of -5, -6, and -7 are for or2txxa devices only. table 37a. or2cxxa and or2txxa asynchronous memory read during write operation (ma/mb modes) or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max read during write operation (t j = 85 c, v dd = min): write enable (wren) to pfu output delay (a4/b4 to f[3:0]) write-port enable (wpe) to pfu output delay (c0 to f[3:0]) data to pfu output delay (wd[3:0] to f[3:0]) mem*_wrdel mem*_pwrdel mem*_ddel 7.0 9.0 5.0 4.9 6.4 3.6 4.8 5.8 3.1 3.9 4.7 2.5 4.0 4.7 2.5 3.9 4.5 2.2 ns ns ns table 37b. or2txxb asynchronous memory read during write operation (ma/mb modes) or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max read during write operation (t j = +85 c, v dd = min): write enable (wren) to pfu output delay (a4/b4 to f[3:0]) write-port enable (wpe) to pfu output delay (c0 to f[3:0]) data to pfu output delay (wd[3:0] to f[3:0]) mem*_wrdel mem*_pwrdel mem*_ddel 4.5 4.6 2.7 3.9 4.0 2.4 ns ns ns
data sheet orca series 2 fpgas june 1999 142 lucent technologies inc. timing characteristics (continued) 5-3229(f).r6 figure 58. read during write a[3:0], b[3:0] a4, b4 (wren) wd[3:0] f[3:0] wd[3:0] f[3:0] t pw mem*_wrdel mem*_ddel mem*_wrdel data stable during wren and wpe data changing during wren and wpe co (wpe) mem*_pwrdel mem*_pwrdel
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 143 timing characteristics (continued) note: speed grades of -5, -6, and -7 are for or2txxa devices only. table 38a. or2cxxa and or2txxa asynchronous memory read during write, clocking data into latch/ flip-flop (ma/mb modes) or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max setup time (tj = 85 c, v dd = min): address to clock (a[3:0], b[3:0] to ck) write enable (wren) to clock (a4/b4 to ck) write-port enable (wpe) to clock (c0 to ck) data (wd[3:0] to ck) mem*_aset mem*_wrset mem*_pwrset mem*_dset 2.4 5.4 7.4 3.5 1.8 4.4 5.9 2.6 1.2 3.8 4.8 2.6 1.1 3.4 4.3 2.3 1.0 3.1 4.0 2.2 1.0 3.0 3.9 2.1 ns ns ns ns hold time (tj = all, v dd = all): all th 0.0 0.0 0.0 0.0 0.0 0.0 ns clock to pfu out (ck to q[3:0])register reg_del 2.4 2.0 1.9 1.5 1.3 1.0 ns table 38b. or2txxb asynchronous memory read during write, clocking data into latch/flip-flop (ma/mb modes) or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max setup time (t j = 85 c, v dd = min): address to clock (a[3:0], b[3:0] to ck) write enable (wren) to clock (a4/b4 to ck) write-port enable (wpe) to clock (c0 to ck) data (wd[3:0] to ck) mem*_aset mem*_wrset mem*_pwrset mem*_dset 0.9 2.9 3.7 2.0 0.8 2.5 3.2 1.7 ns ns ns ns hold time (t j = all, v dd = all): all th 0.0 0.0 ns clock to pfu out (ck to q[3:0])register reg_del 1.0 1.0 ns
data sheet orca series 2 fpgas june 1999 144 lucent technologies inc. timing characteristics (continued) 5-3230(f).r6 figure 59. read during writeclocking data into flip-flop a[3:0], b[3:0] a4, b4 (wren) wd[3:0] ck t pw mem*_dset q[3:0] mem*_aset reg_del c0 (wpe) mem*_pwrset mem*_wrset
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 145 timing characteristics (continued) 1. readback of the configuration bit stream when simultaneously writing to a pfu in either sspm fast mode or sdpm fast mode is n ot allowed. 2. because the setup time of data into the latches/ffs is less than 0 ns, data written into the ram can be loaded into a latch/f f in the same pfu on the next opposite clock edge (one-half clock period). note: speed grades of -5, -6, and -7 are for or2txxa devices only. table 39a. or2cxxa and or2txxa synchronous memory write characteristics (sspm and sdpm modes) or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max write operation for fast-ram mode 1 : maximum frequency clock low time clock high time clock to data valid (ck to f[3:0]) 2 ffsck tfscl tfsch fmems_del 38.2 13.1 13.1 9.0 52.6 9.5 9.5 7.4 83.3 6.0 6.0 6.2 90.9 5.5 5.5 5.0 92.6 5.4 5.4 5.3 96.2 5.2 5.2 5.2 mhz ns ns ns write operation for normal ram mode: maximum frequency clock low time clock high time clock to data valid (ck to f[3:0]) fsck tscl tsch mems_del 24.3 20.6 20.6 10.9 33.3 15.0 15.0 8.6 52.6 9.5 9.5 7.5 58.0 8.5 8.5 6.0 58.8 8.5 8.5 6.4 59.8 8.4 8.4 5.9 mhz ns ns ns write operation setup time: address to clock (a[3:0]/b[3:0] to ck) data to clock (wd[3:0] to ck) write enable (wren) to clock (a4 to ck) write-port enable (wpe) to clock (c0 to ck) mems_aset mems_dset mems_wrset mems_pwrset 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns ns ns write operation hold time: address to clock (a[3:0]/b[3:0] to ck) data to clock (wd[3:0] to ck) write enable (wren) to clock (a4 to ck) write-port enable (wpe) to clock (c0 to ck) mems_ahld mems_dhld mems_wrhld mems_pwrhld 3.8 3.8 3.8 3.3 3.0 3.0 3.0 2.3 2.2 2.2 2.2 1.5 2.0 2.0 2.0 1.4 1.9 1.9 1.9 1.9 1.8 1.8 1.8 1.2 ns ns ns ns table 39.b or2txxb synchronous memory write characteristics (sspm and sdpm modes) or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max write operation for fast-ram mode 1 : maximum frequency clock low time clock high time clock to data valid (ck to f[3:0]) 2 f fsck t fscl t fsch fmems_del 97.7 5.1 5.1 5.1 112.4 4.5 4.5 4.5 mhz ns ns ns write operation for normal ram mode: maximum frequency clock low time clock high time clock to data valid (ck to f[3:0]) f sck t scl t sch mems_del 60.8 8.2 8.2 5.1 69.9 7.2 7.2 4.5 mhz ns ns ns
data sheet orca series 2 fpgas june 1999 146 lucent technologies inc. 1. readback of the configuration bit stream when simultaneously writing to a pfu in either sspm fast mode or sdpm fast mode is n ot allowed. 2. because the setup time of data into the latches/ffs is less than 0 ns, data written into the ram can be loaded into a latch/f f in the same pfu on the next opposite clock edge (one-half clock period). note: speed grades of -5, -6, and -7 are for or2txxa devices only. 5-4621(f).a figure 60. synchronous memory write characteristics write operation setup time: address to clock (a[3:0]/b[3:0] to ck) data to clock (wd[3:0] to ck) write enable (wren) to clock (a4 to ck) write-port enable (wpe) to clock (c0 to ck) mems_aset mems_dset mems_wrset mems_pwrset 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns ns ns write operation hold time: address to clock (a[3:0]/b[3:0] to ck) data to clock (wd[3:0] to ck) write enable (wren) to clock (a4 to ck) write-port enable (wpe) to clock (c0 to ck) mems_ahld mems_dhld mems_wrhld mems_pwrhld 1.0 1.0 1.0 0.7 0.8 0.8 0.8 0.6 ns ns ns ns table 39.b or2txxb synchronous memory write characteristics (sspm and sdpm modes) (continued) or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max ck f[3:0] a[3:0], b[3:0] wd[3:0] mems_aset a4 (wren) mems_ahld mems_dset mems_dhld mems_wrset mems_wrhld mems_pwrset mems_pwrhld c0 (wpe) t fsch /t sch t fscl /t scl fmems_del/mems_del timing characteristics (continued)
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 147 timing characteristics (continued) note: speed grades of -5, -6, and -7 are for or2txxa devices only. 5-4622(f).r2.a figure 61. synchronous memory read cycle table 40a. or2cxxa and or2txxa synchronous memory read characteristics (sspm and sdpm modes) or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max read operation (t j = 85 c, v dd = min): read cycle time data valid after address (a[3:0], b[3:0] to f[3:0]) t rc mems*_adel 5.1 4.0 3.6 2.8 2.7 2.1 2.4 1.7 2.3 1.4 2.0 1.1 ns ns read operation, clocking data into latch/ff (t j = 85 c, v dd = min): address to clock setup time (a[3:0], b[3:0] to ck) clock to pfu outputregister (ck to q[3:0]) mems*_aset reg_del 2.4 2.4 1.8 2.0 1.2 1.9 1.1 1.5 1.0 1.3 0.9 1.0 ns ns table 40b. or2txxb synchronous memory read characteristics (sspm and sdpm modes) or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max read operation (t j = 85 c, v dd = min): read cycle time data valid after address (a[3:0], b[3:0] to f[3:0]) t rc mems*_adel 1.9 1.8 1.8 1.4 ns ns read operation, clocking data into latch/ff (t j = 85 c, v dd = min): address to clock setup time (a[3:0], b[3:0] to ck) clock to pfu outputregister (ck to q[3:0]) mems*_aset reg_del 0.9 1.0 0.8 1.0 ns ns a[3:0], b[3:0] f[3:0] ck q[3:0] mem*_adel reg_del mem*_aset
data sheet orca series 2 fpgas june 1999 148 lucent technologies inc. timing characteristics (continued) note: speed grades of -5, -6, and -7 are for or2txxa devices only. table 41a. or2cxxa and or2txxa pfu output mux, plc bidi, and direct routing timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max pfu output mux (t j = 85 c, v dd = min) output mux delay (f[3:0]/q[3:0] to o[4:0]) omux_del 1.1 0.8 0.6 0.5 0.4 0.4 ns plc 3-statable bidis (t j = 85 c, v dd = min) bidi propagation delay bidi 3-state enable/disable delay tri_del trien_del 1.2 1.7 1.0 1.3 0.8 1.0 0.7 0.8 0.6 0.8 0.5 0.7 ns ns direct routing (t j = 85 c, v dd = min) pfu to pfu delay (xsw) pfu feedback (xsw) dir_del fdbk_del 1.4 1.0 1.1 0.8 0.9 0.7 0.7 0.6 0.6 0.5 0.6 0.5 ns ns table 41b. or2txxb pfu output mux, plc bidi, and direct routing timing characteristics or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max pfu output mux (t j = 85 c, v dd = min) output mux delay (f[3:0]/q[3:0] to o[4:0]) omux_del 0.4 0.4 ns plc 3-statable bidis (t j = 85 c, v dd = min) bidi propagation delay bidi 3-state enable/disable delay tri_del trien_del 0.7 1.1 0.6 0.9 ns ns direct routing (t j = 85 c, v dd = min) pfu to pfu delay (xsw) pfu feedback (xsw) dir_del fdbk_del 0.6 0.4 0.5 0.4 ns ns
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 149 timing characteristics (continued) notes: this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. speed grades of -5, -6, and -7 are for or2txxa devices only. note: this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. table 42a. or2cxxa and or2txxa internal clock delay or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. device (t j = 85 c, v dd = min) symbol speed unit -2 -3 -4 -5 -6 -7 minmaxminmaxminmaxminmaxminmaxminmax or2c04a/or2t04a clk_del 4.6 4.4 4.3 3.6 ns or2c06a/or2t06a clk_del 4.7 4.5 4.4 3.7 ns or2c08a/or2t08a clk_del 4.8 4.6 4.5 3.8 ns or2c10a/or2t10a clk_del 4.9 4.7 4.6 3.9 ns or2c12a/or2t12a clk_del 5.0 4.8 4.7 4.0 ns or2c15a/or2t15a clk_del 5.1 4.9 4.8 4.1 3.9 3.3 ns or2c26a/or2t26a clk_del 5.2 5.1 5.0 4.2 4.0 3.4 ns or2c40a/or2t40a clk_del 5.6 5.4 5.3 4.5 4.2 3.6 ns table 42b. or2txxb internal clock delay or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. device (t j = 85 c, v dd = min) symbol speed unit -7 -8 min max min max or2t15b clk_del 3.6 3.1 ns or2t40b clk_del 3.8 3.3 ns
data sheet orca series 2 fpgas june 1999 150 lucent technologies inc. timing characteristics (continued) notes: the pin-to-pin timing information from orca foundry version 9.2 and later is more accurate than this table. for earlier versions of orca foundry, the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay, the clock routing to the pfu clk input, the clock ? q of the ff, and the delay through the output buffer. the delay will be reduced if any of the clock branches are not used. the given timing requires that the input clock pin be located at one of the four center pics on any side of the devic e and that the direct ff ? i/o routing be used. if the clock pin is not located at one of the four center pics, this delay must be increased by up to the following amounts: or2c/2t04a = 1.5%, or2c/2t06a = 2.0%, or2c/2t08a = 3.1%, or2c/2t10a = 3.9%, or2c/2t12a = 4.9%, or2c/2t15a = 5.7%, or2c/2t26a = 8.1%, or2c/2t40a = 12.5%. speed grades of -5, -6, and -7 are for or2txxa devices only. table 43a. or2cxxa and or2txxa or2cxxa/or2txxa global clock to output delay (pin-to-pin)output on same side of the device as the clock pin or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; industrial: v dd = 5.0 v 10%, C40 c t a +85 c; c l = 50 pf. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c; c l = 50 pf. description (t j = 85 c, v dd = min) device speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max clk input pin ? output pin (fast) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 11.7 11.8 11.9 12.0 12.1 12.2 12.3 12.7 10.3 10.4 10.5 10.6 10.7 10.8 11.0 11.4 9.8 9.9 10.0 10.1 10.2 10.3 10.5 10.8 8.6 8.7 8.8 8.9 9.0 9.1 9.2 9.5 8.3 8.4 8.6 6.7 6.9 7.0 ns ns ns ns ns ns ns ns clk input pin ? output pin (slewlim) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 13.9 14.0 14.1 14.2 14.3 14.4 14.5 14.9 12.5 12.6 12.7 12.8 12.9 13.0 13.2 13.6 11.7 11.8 11.9 12.0 12.1 12.2 12.3 12.6 10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.9 9.5 9.6 9.8 7.4 7.5 7.7 ns ns ns ns ns ns ns ns clk input pin ? output pin (sinklim) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 15.7 15.8 15.9 16.0 16.1 16.2 16.3 16.7 14.7 14.8 14.9 15.0 15.1 15.2 15.3 15.7 13.7 13.8 13.9 14.0 14.1 14.2 14.3 14.6 13.1 13.2 13.3 13.4 13.5 13.6 13.7 14.0 12.1 12.2 12.4 10.0 10.7 10.9 ns ns ns ns ns ns ns ns
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 151 timing characteristics (continued) notes: the pin-to-pin timing information from orca foundry version 9.2 and later is more accurate than this table. for earlier versions of orca foundry, the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay, the clock routing to the pfu clk input, the clock ? q of the ff, and the delay through the output buffer. the delay will be reduced if any of the clock branches are not used. the given timing requires that the input clock pin be located at one of the four center pics on any side of the device an d that the direct ff ? i/o routing be used. if the clock pin is not located at one of the four center pics, this delay must be increased by up to the following amounts: or2t15b = 5.7%, or2t40b = 12.5%. figure 62. global clock to output delay table 43b. or2txxb global clock to output delay (pin-to-pin)output on same side of the device as the clock pin or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c; c l =50 pf. description (t j = 85 c, v dd = min) device speed unit -7 -8 min max min max clk input pin ? output pin (fast) or2t15b or2t40b 7.3 7.5 6.6 6.6 ns ns clk input pin ? output pin (slewlim) or2t15b or2t40b 8.2 8.4 7.4 7.6 ns ns clk input pin ? output pin (sinklim) or2t15b or2t40b 12.9 13.1 12.1 12.3 ns ns 5-4846(f) output (50 pf load) q d clk
data sheet orca series 2 fpgas june 1999 152 lucent technologies inc. timing characteristics (continued) notes: the pin-to-pin timing information from orca foundry version 9.2 and later is more accurate than this table. for earlier versions of orca foundry, the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay, the clock routing to the pfu clk input, the clock ? q of the ff, and the delay through the output buffer. the delay will be reduced if any of the clock branches are not used. the given timing requires that the input clock pin be located at one of the four center pics on any side of the device an d that the direct ff ? i/o routing be used. if the clock pin is not located at one of the four center pics, this delay must be increased by up to the following amounts: or2c/2t04a = 1.5%, or2c/2t06a = 2.0%, or2c/2t08a = 3.1%, or2c/2t10a = 3.9%, or2c/2t12a = 4.9%, or2c/2t15a = 5.7%, or2c/2t26a = 8.1%, or2c/2t40a = 12.5%. speed grades of -5, -6, and -7 are for or2txxa devices only table 44a. or2cxxa/or2txxa global clock to output delay (pin-to-pin)output not on same side of the device as the clock pin or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; industrial: v dd = 5.0 v 10%, C40 c t a +85 c; c l = 50 pf. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c; c l = 50 pf. description (t j = 85 c, v dd = min) device speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max clk input pin ? output pin (fast) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 11.8 12.0 12.2 12.4 12.6 12.8 13.1 14.4 10.5 10.6 10.8 11.0 11.2 11.5 11.9 13.3 9.9 10.0 10.1 10.3 10.5 10.7 11.1 12.4 8.8 8.9 9.0 9.2 9.4 9.6 10.0 11.1 8.9 9.3 10.5 7.3 7.7 8.3 ns ns ns ns ns ns ns ns clk input pin ? output pin (slewlim) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 14.1 14.3 14.4 14.6 14.8 15.0 15.3 16.7 12.7 12.9 13.1 13.3 13.5 13.6 14.1 15.5 11.8 11.9 12.0 12.2 12.4 12.6 12.9 14.2 10.3 10.4 10.5 10.6 10.8 11.0 11.4 12.5 10.1 10.5 11.7 8.0 8.4 9.1 ns ns ns ns ns ns ns ns clk input pin ? output pin (sinklim) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 15.9 16.0 16.2 16.4 16.6 16.8 17.1 18.5 14.8 15.0 15.2 15.4 15.6 15.8 16.2 17.6 13.8 13.9 14.1 14.2 14.4 14.6 14.9 16.3 13.4 13.5 13.6 13.7 13.9 14.1 14.4 15.6 12.7 13.1 14.3 11.2 11.6 12.2 ns ns ns ns ns ns ns ns
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 153 . timing characteristics (continued) notes: the pin-to-pin timing information from orca foundry version 9.2 and later is more accurate than this table. for earlier versions of orca foundry, the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay, the clock routing to the pfu clk input, the clock ? q of the ff, and the delay through the output buffer. the delay will be reduced if any of the clock branches are not used. the given timing requires that the input clock pin be located at one of the four center pics on any side of the device an d that the direct ff ? i/o routing be used. if the clock pin is not located at one of the four center pics, this delay must be increased by up to the following amounts: or2t15b = 5.7%, or2t40b = 12.5%. figure 63. global clock to output delay table 44b. or2txxb global clock to output delay (pin-to-pin)output not on same side of the device as the clock pin or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c; c l = 50 pf. description (t j = 85 c, v dd = min) device speed unit -7 -8 minmaxminmax clk input pin ? output pin (fast) or2t15b or2t40b 7.6 8.1 6.9 7.4 ns ns clk input pin ? output pin (slewlim) or2t15b or2t40b 8.4 9.0 7.7 8.2 ns ns clk input pin ? output pin (sinklim) or2t15b or2t40b 13.2 13.7 12.4 12.8 ns ns output (50 pf load) q d clk 5-4846(f)
data sheet orca series 2 fpgas june 1999 154 lucent technologies inc. timing characteristics (continued) notes: the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. the given setup (delayed and no delay) and hold (delayed) timing allows the input clock pin to be located in any pic on any side of the device, but direct i/o ? ff routing must be used. the hold (no delay) timing assumes the clock pin is located at one of the four center pics and direct i/o ? ff routing is used. if it is not located at one of the four center pics, this delay must be increased by up to the following amounts: or2c/2t04a = 5.3%, or2c/2t06a = 6.4%, or2c/2 t08a = 7.3%, or2c/2t10a = 9.1%, or2c/2t12a = 10.8%, or2c/2t15a = 12.2%, or2c/2t26a = 16.1%, or2c/2t40a = 21.2%. speed grades of -5, -6, and -7 are for or2txxa devices only. table 45a. or2cxxa/or2txxa global input to clock setup/hold time (pin-to-pin) or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. description (t j = all, v dd = all) device speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max input to clk (ttl/cmos) setup time (no delay) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns ns ns ns ns ns ns input to clk (ttl/cmos) setup time (delayed) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 5.8 5.7 5.6 5.3 5.2 4.9 7.3 6.8 5.5 5.4 5.3 5.0 4.9 4.7 6.9 6.4 4.2 4.1 4.0 3.9 3.8 3.6 6.0 5.5 4.0 3.9 3.8 3.7 3.6 3.4 5.7 5.2 4.1 6.7 6.5 4.1 6.0 5.8 ns ns ns ns ns ns ns ns input to clk (ttl/cmos) hold time (no delay) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 4.2 4.3 4.5 4.8 5.0 5.4 6.2 7.9 4.0 4.1 4.3 4.6 4.8 5.1 5.8 6.8 3.8 3.9 4.1 4.4 4.6 4.9 5.6 6.6 3.6 3.7 3.9 4.2 4.4 4.7 5.3 6.3 4.2 4.6 5.8 3.7 4.1 4.9 ns ns ns ns ns ns ns ns input to clk (ttl/cmos) hold time (delayed) or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2c/2t26a or2c/2t40a 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns ns ns ns ns ns ns
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 155 timing characteristics (continued) notes: the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. the given setup (delayed and no delay) and hold (delayed) timing allows the input clock pin to be located in any pic on any side of the device, but direct i/o ? ff routing must be used. the hold (no delay) timing assumes the clock pin is located at one of the four center pics and direct i/o ? ff routing is used. if it is not located at one of the four center pics, this delay must be increased by up to the following amounts: or2t15b = 5.7%, or2t40b = 12.5%. figure 64. global input to clock setup/hold time table 45b. or2txxb global input to clock setup/hold time (pin-to-pin) or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. description (t j = all, v dd = all) device speed unit -7 -8 min max min max input to clk (ttl/cmos) setup time (no delay) or2t15b or2t40b 0.0 0.0 0.0 0.0 ns ns input to clk (ttl/cmos) setup time (delayed) or2t15b or2t40b 4.7 7.7 4.0 5.5 ns ns input to clk (ttl/cmos) hold time (no delay) or2t15b or2t40b 1.6 1.4 1.4 1.3 ns ns input to clk (ttl/cmos) hold time (delayed) or2t15b or2t40b 0.0 0.0 0.0 0.0 ns ns q d clk input 5-4847(f)
data sheet orca series 2 fpgas june 1999 156 lucent technologies inc. timing characteristics (continued) notes: if the input buffer is placed in delay mode, the chip hold time to the nearest pfu latch is guaranteed to be 0 if the clock is routed using the primary clock network; (t j = all, v dd = all). it should also be noted that any signals routed on the clock lines or using the tridi buffers directly from the input buffer do not get delayed at any time. the delays for all input buffers assume an input rise/fall time of 1 v/ns. speed grades of -5, -6, and -7 are for or2txxa devices only table 46a. or2cxxa/or2txxa programmable i/o cell timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -2 -3 -4 -5 -6 -7 min max min max min max min max min max min max inputs (t j = 85 c, v dd = min) input rise time t r 500 500 500 500 500 500 ns input fall time t f 500 500 500 500 500 500 ns pad to in delay pad_in_del 1.7 1.5 1.3 1.2 1.2 1.1 ns pad to nearest pfu latch output chip_latch 6.2 4.7 4.1 3.5 3.1 2.9 ns delay added to general routing (input buffer in delay mode for or2c/2t15a and smaller devices) 8.1 7.0 6.0 5.9 6.2 5.8 ns delay added to general routing (input buffer in delay mode for or2c/2t26a and or2c/2t40a) 11.0 9.7 8.6 8.6 9.0 8.6 ns delay added to direct-ff routing (input buffer in delay mode for or2c/2t15a and smaller devices) 8.0 6.8 5.9 6.0 6.4 6.0 ns delay added to direct-ff routing (input buffer in delay mode for or2c/2t26a and or2c/2t40a) 10.9 10.2 8.5 8.6 9.1 7.9 ns outputs (t j = 85 c, v dd = min, c l = 50 pf) pfu ck to pad delay (dout[3:0] to pa d ) : fast slewlim sinklim dout_del(f) dout_del(sl) dout_del(si) 7.1 9.4 11.2 6.2 8.4 10.5 5.5 7.4 9.4 5.0 6.4 9.5 4.4 5.6 8.3 3.3 4.1 7.2 ns ns ns output to pad delay (out[3:0] to pa d ) : fast slewlim sinklim out_del(f) out_del(sl) out_del(si) 5.0 6.7 9.8 4.0 6.3 7.2 3.6 5.5 7.5 3.1 4.5 7.6 2.7 3.9 6.5 2.3 3.1 6.2 ns ns ns 3-state enable delay (ts[3:0] to pa d ) : fast slewlim sinklim ts_del(f) ts_del(sl) ts_del(si) 5.8 7.5 10.6 4.7 7.0 7.9 4.0 6.3 8.4 3.5 5.2 9.3 3.1 4.7 8.0 2.5 3.7 7.6 ns ns ns
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 157 . timing characteristics (continued) notes: if the input buffer is placed in delay mode, the chip hold time to the nearest pfu latch is guaranteed to be 0 if the clock is routed using the primary clock network; (t j = all, v dd = all). it should also be noted that any signals routed on the clock lines or using the tridi buffers directly from the input buffer do not get delayed at any time. the delays for all input buffers assume an input rise/fall time of 1 v/ns. table 46b. or2txxb programmable i/o cell timing characteristics or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol speed unit -7 -8 min max min max inputs (t j = 85 c, v dd = min) input rise time t r 500 500 ns input fall time t f 500 500 ns pad to in delay pad_in_del 1.1 1.0 ns pad to nearest pfu latch output chip_latch 3.3 2.4 ns delay added to general routing (input buffer in delay mode for or2t15b and smaller devices) 6.6 6.1 ns delay added to general routing (input buffer in delay mode for or2t40b) 8.9 8.2 ns delay added to direct-ff routing (input buffer in delay mode for or2t15b and smaller devices) 6.4 6.0 ns delay added to direct-ff routing (input buffer in delay mode for or2t40b) 8.7 8.0 ns outputs (t j = 85 c, v dd = min, c l = 50 pf) pfu ck to pad delay (dout[3:0] to pa d ) : fast slewlim sinklim dout_del(f) dout_del(sl) dout_del(si) 2.8 3.6 8.3 2.5 3.3 8.0 ns ns ns output to pad delay (out[3:0] to pa d ) : fast slewlim sinklim out_del(f) out_del(sl) out_del(si) 2.8 3.6 8.3 2.5 3.3 8.0 ns ns ns 3-state enable delay (ts[3:0] to pa d ) : fast slewlim sinklim ts_del(f) ts_del(sl) ts_del(si) 3.0 3.8 9.1 2.7 3.4 8.7 ns ns ns
data sheet orca series 2 fpgas june 1999 158 lucent technologies inc. timing characteristics (continued) table 47. series 2 general configuration mode timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa/b commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa/b industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit all configuration modes m[3:0] setup time to init high t smode 50.0 ns m[3:0] hold time from init high t hmode 600.0 ns reset pulse width low to start reconfiguration t rw 50.0 ns prgm pulse width low to start reconfiguration t pgw 50.0 ns master and asynchronous peripheral modes power-on reset delay cclk period (m3 = 0) (m3 = 1) configuration latency (noncompressed): or2c/2t04a (m3 = 0) (m3 = 1) or2c/2t06a (m3 = 0) (m3 = 1) or2c/2t08a (m3 = 0) (m3 = 1) or2c/2t10a (m3 = 0) (m3 = 1) or2c/2t12a (m3 = 0) (m3 = 1) or2c/2t15a/2t15b (m3 = 0) (m3 = 1) or2c/2t26a (m3 = 0) (m3 = 1) or2c/2t40a/2t40b (m3 = 0) (m3 = 1) t po t cclk t cl 17.30 66.0 528.00 4.31 34.48 6.00 48.00 7.62 60.96 9.82 78.56 11.86 94.88 14.57 116.56 20.25 162.00 31.29 250.32 69.47 265.00 2120.00 17.30* 138.40* 24.08* 192.64* 30.60* 244.80* 39.43* 315.44* 47.62* 380.96* 58.51* 468.08* 81.32* 650.56* 125.62* 1004.96* ms ns ns ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms slave serial and synchronous peripheral modes power-on reset delay cclk period (or2cxxa/or2txxa) cclk period (or2txxb) configuration latency (noncompressed): or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2t15b or2c/2t26a or2c/2t40a or2t40b t po t cclk t cclk t cl 4.33 100.00 25.00 6.53 9.09 11.55 14.88 17.97 22.08 5.52 30.69 47.40 11.85 17.37 ms ns ns ms ms ms ms ms ms ms ms ms ms * not applicable to asynchronous peripheral mode.
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 159 note: t po is triggered when v dd reaches between 3.0 v to 4.0 v for the or2cxxa and between 2.7 v and 3.0 v for the or2txxa/or2txxb. slave parallel mode power-on reset delay cclk period (or2cxxa/or2txxa) cclk period (or2txxb) configuration latency (noncompressed): or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a or2t15b or2c/2t26a or2c/2t40a or2t40b t po t cclk t cclk t cl 4.33 100.00 25.0 0.82 1.14 1.44 1.86 2.25 2.76 0.69 3.84 5.93 1.48 17.37 ms ns ns ms ms ms ms ms ms ms ms ms ms partial reconfiguration (noncompressed): or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a/2t15b or2c/2t26a or2c/2t40a/2t40b t pr 1.70 2.00 2.20 2.50 2.70 3.00 3.50 4.30 s/frame s/frame s/frame s/frame s/frame s/frame s/frame s/frame init timing init high to cclk delay: slave parallel slave serial synchronous peripheral master serial: (m3 = 1) (m3 = 0) master parallel: (m3 = 1) (m3 = 0) t init_clk 1.00 1.00 1.00 1.06 0.59 5.28 1.12 4.51 2.65 21.47 4.77 s s s s s s s initialization latency ( prgm high to init high): or2c/2t04a or2c/2t06a or2c/2t08a or2c/2t10a or2c/2t12a or2c/2t15a/2t15b or2c/2t26a or2c/2t40a/2t40b t il 63.36 74.98 86.59 98.21 109.82 121.44 144.67 181.90 254.40 301.04 347.68 394.32 440.96 487.60 580.88 730.34 s s s s s s s s init high to wr , asynchronous peripheral t init_wr 1.50 s timing characteristics (continued) table 47. series 2 general configuration mode timing characteristics (continued) or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa/b commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa/b industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit
data sheet orca series 2 fpgas june 1999 160 lucent technologies inc. timing characteristics (continued) series 2 figure 65. general configuration mode timing diagram 5-4531(f) v dd cclk m[3:0] prgm init t po + t il t il t cclk t smode t hmode t init_clk done t cl t pgw
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 161 timing characteristics (continued) note: serial configuration data is transmitted out on dout on the falling edge of cclk after it is input din. figure 66. master serial configuration mode timing diagram table 48. series 2 master serial configuration mode timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa/b commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa/b industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min nom max unit din setup time t s 60.0 ns din hold time t h 0ns cclk frequency (m3 = 0) f c 3.8 10.0 15.2 mhz cclk frequency (m3 = 1) f c 0.48 1.25 1.9 mhz cclk to dout delay t d 30ns 5-4532(f) din cclk dout t s t h bit n t d bit n
data sheet orca series 2 fpgas june 1999 162 lucent technologies inc. timing characteristics (continued) notes: the rclk period consists of seven cclks for rclk low and one cclk for rclk high. serial data is transmitted out on dout 1.5 cclk cycles after the byte is input d[7:0] f.44(f) figure 67. master parallel configuration mode timing diagram table 49. series 2 master parallel configuration mode timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa/b commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa/b industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit rclk to address valid t av 0 200 ns d[7:0] setup time to rclk high t s 60 ns d[7:0] hold time to rclk high t h 0ns rclk low time (m3 = 0) t cl 462 1855 ns rclk high time (m3 = 0) t ch 66 265 ns rclk low time (m3 = 1) t cl 3696 14840 ns rclk high time (m3 = 1) t ch 528 2120 ns cclk to dout t d 30ns a[17:0] rclk d[7:0] t cl t ch t av cclk dout t h t s byte n byte n + 1 d0 d1 d2 d3 d4 d5 d6 d7 t d
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 163 timing characteristics (continued) * this parameter is valid whether the end of not rdy is determined from the rdy/rclk pin or from the d7 pin. notes: serial data is transmitted out on dout on the falling edge of cclk after the byte is input d[7:0]. d[6:0] timing is the same as the write data port of the d7 waveform because d[6:0] are not enabled. figure 68. asynchronous peripheral configuration mode timing diagram table 50. series 2 asynchronous peripheral configuration mode timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa/b commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa/b industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit wr , cs0 , and cs1 pulse width t wr 100 ns d[7:0] setup time t s 20 ns d[7:0] hold time t h 0ns rdy delay t rdy 60ns rdy low t b 18cclk periods earliest wr after rdy goes high* t wr2 0ns rd to d7 enable/disable t den 60ns cclk to dout t d 30ns 5-4533.a cs1 d7 cclk dout cs0 rdy d0 d1 d2 t b t wr t s t h t rdy wr d7 t d previous byte t wr2 write data d3 t den t den rd
data sheet orca series 2 fpgas june 1999 164 lucent technologies inc. timing characteristics (continued) note: serial data is transmitted out on dout 1.5 clock cycles after the byte is input d[7:0]. note: serial data is transmitted out on dout 1.5 clock cycles after the byte is input d[7:0]. figure 69. synchronous peripheral configuration mode timing diagram table 51a. or2cxxa/or2txxa synchronous peripheral configuration mode timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit d[7:0] setup time t s 20 ns d[7:0] hold time t h 0ns cclk high time t ch 50 ns cclk low time t cl 50 ns cclk frequency f c 10mhz cclk to dout t d 30ns table 51b. or2txxb synchronous peripheral configuration mode timing characteristics or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit d[7:0] setup time t s 15 ns d[7:0] hold time t h 0ns cclk high time t ch 12.5 ns cclk low time t cl 12.5 ns cclk frequency f c 40mhz cclk to dout t d 10ns 5-4534(f) cclk init d[7:0] dout rdy 01234 byte 0 byte 1 t init_clk t ch t cl t h t s t d 5 6 7 0
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 165 timing characteristics (continued) note: serial configuration data is transmitted out on dout on the falling edge of cclk after it is input on din. note: serial configuration data is transmitted out on dout on the falling edge of cclk after it is input on din figure 70. slave serial configuration mode timing diagram table 52a. or2cxxa/or2txxa slave serial configuration mode timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c parameter symbol min max unit din setup time t s 20 ns din hold time t h 0ns cclk high time t ch 50 ns cclk low time t cl 50 ns cclk frequency f c 10mhz cclk to dout t d 30ns table 52b. or2txxb slave serial configuration mode timing characteristics or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit din setup time t s 15 ns din hold time t h 0ns cclk high time t ch 12.5 ns cclk low time t cl 12.5 ns cclk frequency f c 40mhz cclk to dout t d 10ns 5-4535(f) din cclk dout t d t s t h t cl t ch bit n bit n
data sheet orca series 2 fpgas june 1999 166 lucent technologies inc. timing characteristics (continued) note: daisy chaining of fpgas is not supported in this mode. note: daisy chaining of fpgas is not supported in this mode. figure 71. slave parallel configuration mode timing diagram table 53a. or2cxxa/or2txxa slave parallel configuration mode timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit cs0 , cs1, wr setup time t s1 60 ns cs0 , cs1, wr hold time t h1 20 ns d[7:0] setup time t s2 20 ns d[7:0] hold time t h2 0ns cclk high time t ch 50 ns cclk low time t cl 50 ns cclk frequency f c 10mhz table 53b. or2txxb slave parallel configuration mode timing characteristics or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit cs0 , cs1, wr setup time t s1 cs0 , cs1, wr hold time t h1 15 ns d[7:0] setup time t s2 15 ns d[7:0] hold time t h2 0ns cclk high time t ch 12.5 ns cclk low time t cl 12.5 ns cclk frequency f c 40mhz 5-2848(f) t s1 t h1 t s2 t h2 cs1 cclk d[7:0] cs0 wr
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 167 timing characteristics (continued) figure 72. readback timing diagram table 54. series 2 readback timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa/b commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa/b industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit rd_cfgn to cclk setup time t s 50 ns rd_cfgn high width to abort readback t rba 2cclk cclk low time t cl 50 ns cclk high time t ch 50 ns cclk frequency f c 10mhz cclk to rd_data delay t d 50ns 5-4536(f) t d t ch cclk rd_data t s t cl rd_cfgn bit 0 bit 1 bit 0 t rba
data sheet orca series 2 fpgas june 1999 168 lucent technologies inc. timing characteristics (continued) bstd(f).2c.r3 figure 73. boundary-scan timing diagram table 55. series 2 boundary-scan timing characteristics or2cxxa commercial: v dd = 5.0 v 5%, 0 c t a 70 c; or2cxxa industrial: v dd = 5.0 v 10%, C40 c t a +85 c. or2txxa commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxa industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. or2txxb commercial: v dd = 3.0 v to 3.6 v, 0 c t a 70 c; or2txxb industrial: v dd = 3.0 v to 3.6 v, C40 c t a +85 c. parameter symbol min max unit tdi/tms to tck setup time t s 25 ns tdi/tms hold time from tck t h 0ns tck low time t cl 50 ns tck high time t ch 50 ns tck to tdo delay t d 20ns tck frequency t tck 10mhz tck tms tdi tdo t s t h t d
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 169 measurement conditions 5-3234(f).r1 figure 74. ac test loads 5-3233(f).ar4 figure 75. output buffer delays 5-3235(f).a figure 76. input buffer delays 50 pf a. load used to measure propagation delay to the output under test to the output under test 50 pf v cc gnd 1 k w b. load used to measure rising/falling edges v dd t phh v dd /2 v ss out[i] pa d out 1.5 v 0.0 v t pll pad out[i] ac test loads (shown above) ts[i] out 0.0 v 1.5 v t phh t pll pa d in[i] in 3.0 v v ss v dd /2 v dd pa d i n in[i]
lucent technologies inc. 170 data sheet june 1999 orca series 2 fpgas output buffer characteristics or2cxxa 5-4634(f) figure 77. sinklim (t j = 25 c, v dd = 5.0 v) 5-4636(f) figure 78. slewlim (t j = 25 c, v dd = 5.0 v) 5-4638(f) figure 79. fast (t j = 25 c, v dd = 5.0 v) 5-4635(f) figure 80. sinklim (t j = 125 c, v dd = 4.5 v) 5-4637(f) figure 81. slewlim (t j = 125 c, v dd = 4.5 v) 5-4639(f) figure 82. fast (t j = 125 c, v dd = 4.5 v) 70 60 50 40 30 20 10 0 output current, i o (ma) 012345 output voltage, v o (v) i ol i oh 250 225 150 100 50 0 output current, i o (ma) 0123 4 output voltage, v o (v) i ol i oh 5 200 175 125 75 25 250 225 150 100 50 0 output current, i o (ma) 0123 4 output voltage, v o (v) i ol i oh 5 200 175 125 75 25 50 40 30 20 10 0 output current, i o (ma) 01234 output voltage, v o (v) i ol i oh 5 150 125 100 75 50 0 output current, i o (ma) 01 2 3 4 output voltage, v o (v) i ol i oh 25 175 125 100 75 50 0 output current, i o (ma) 01 2 3 4 output voltage, v o (v) i ol i oh 25 150
171 lucent technologies inc. data sheet orca series 2 fpgas june 1999 output buffer characteristics (continued) or2txxa 5-4637(f) figure 83. sinklim (t j = 25 c, v dd = 3.3 v) 5-4637(f) figure 84. slewlim (t j = 25 c, v dd = 3.3 v) 5-4637(f) figure 85. fast (t j = 25 c, v dd = 3.3 v) 5-4637(f) figure 86. sinklim (t j = 125 c, v dd = 3.0 v) 5-4637(f) figure 87. slewlim (t j = 125 c, v dd = 3.0 v) 5-4637(f) figure 88. fast (t j = 125 c, v dd = 3.0 v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 20 40 60 80 output voltage, v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 60 100 120 140 output voltage, v o (v) output current, i o (ma) i ol i oh 80 40 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 60 100 120 140 output voltage, v o (v) output current, i o (ma) i ol i oh 80 40 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 30 40 output voltage, v o (v) output current, i o (ma) i ol i oh 25 20 15 35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 70 output voltage, v o (v) output current, i o (ma) i ol i oh 50 40 30 60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 70 output voltage, v o (v) output current, i o (ma) i ol i oh 50 40 30 60
lucent technologies inc. 172 data sheet june 1999 orca series 2 fpgas output buffer characteristics (continued) or2txxb 5-7927(f).r1 fi g ure 89. sinklim ( t j = 25 c, v dd = 3.3 v ) 5-7928(f).r1 fi g ure 90. slewlim ( t j = 25 c, v dd = 3.3 v ) 5-7929(f).r1 figure 91. fast (t j = 25 c, v dd = 3.3 v) 5-7930(f).r1 fi g ure 92. sinklim ( t j = 125 c, v dd = 3.0 v ) 5-7931(f).r1 fi g ure 93. slewlim ( t j = 125 c, v dd = 3.0 v ) 5-7932(f).r1 fi g ure 94. fast ( t j = 125 c, v dd = 3.0 v ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 90 80 i ol 60 50 40 30 20 10 0 output voltage, v o (v) output current, i o (ma) i oh 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 180 160 140 120 100 80 60 40 20 0 output voltage, v o (v) output current, i o (ma) i ol i oh 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 180 160 140 120 100 80 60 40 20 0 output voltage, v o (v) output current, i o (ma) i ol i oh 0.0 0.5 1.0 1.5 2.0 2.5 3.0 55 50 40 30 25 20 15 10 05 0 output voltage, v o (v) output current, i o (ma) 45 35 i ol i oh 0.0 0.5 1.0 1.5 2.0 2.5 3.0 110 100 80 60 50 40 30 20 10 0 output voltage, v o (v) output current, i o (ma) 90 70 i ol i oh 0.0 0.5 1.0 1.5 2.0 2.5 3.0 110 100 80 60 50 40 30 20 10 0 output voltage, v o (v) output current, i o (ma) 90 70 i ol i oh
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 173 package outline drawings terms and definitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. typical (typ): when specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified.
data sheet orca series 2 fpgas june 1999 174 lucent technologies inc. package outline drawings (continued) 84-pin plcc dimensions are in millimeters. 5-2347r.16 1.27 typ 0.330/0.533 0.10 seating plane 0.51 min typ 5.080 max pin #1 identifier zone 11 75 53 33 12 32 54 74 29.083 0.076 30.353 max 30.353 max 1 29.083 0.076
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 175 package outline drawings (continued) 100-pin tqfp dimensions are in millimeters. 5-2146r.15 0.50 typ 1.60 max seating plane 0.08 1.40 0.05 0.05/0.15 detail a detail b 14.00 0.20 16.00 0.20 76 100 1 25 26 50 51 75 14.00 0.20 16.00 0.20 pin #1 identifier zone detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25
data sheet orca series 2 fpgas june 1999 176 lucent technologies inc. package outline drawings (continued) 144-pin tqfp dimensions are in millimeters. 5-3815r.5 detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 1.60 max seating plane 0.08 0.50 typ 1.40 0.05 0.05/0.15 detail a detail b pin #1 identifier zone 20.00 0.20 22.00 0.20 109 144 1 36 37 72 73 108 20.00 0.20 22.00 0.20
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 177 package outline drawings (continued) 160-pin qfp dimensions are in millimeters. 5-2132r.12 81 120 28.00 0.20 31.20 0.20 detail a detail b 4.07 max 0.65 typ seating plane 0.10 3.42 0.25 0.25 min 1 40 121 160 pin #1 identifier zone 31.20 0.20 28.00 0.20 80 41 0.22/0.38 0.12 m 0.13/0.23 detail b 0.25 0.73/1.03 1.60 ref gage plane seating plane detail a
data sheet orca series 2 fpgas june 1999 178 lucent technologies inc. package outline drawings (continued) 208-pin sqfp dimensions are in millimeters. 5-2196r.13 156 105 30.60 0.20 157 208 1 52 53 104 28.00 0.20 28.00 0.20 30.60 0.20 pin #1 identifier zone 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 179 package outline drawings (continued) 208-pin sqfp2 dimensions are in millimeters. 5-3828.a 156 105 30.60 0.20 157 208 1 52 53 104 28.00 0.20 exposed heat sink appears on bottom surface: chip bonded face up (see detail c) 28.00 0.20 30.60 0.20 pin #1 identifier zone 21.0 ref 21.0 ref 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.2 0.1 0 m 0.090/0.200
data sheet orca series 2 fpgas june 1999 180 lucent technologies inc. package outline drawings (continued) 240-pin sqfp dimensions are in millimeters. 5-2718r.8 0.08 3.40 0.20 s eating pla ne 0.25 min 0.50 typ detail a detail b 180 121 181 240 34.60 0.20 1 32.00 0.20 60 61 120 pin #1 identifier zone 32.00 0.20 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 4.10 max 34.60 0.20
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 181 package outline drawings (continued) 240-pin sqfp2 dimensions are in millimeters. 5-3825r.8 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 chip chip bonded face up copper heat sink 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail a detail b 180 121 181 240 34.60 0.20 1 32.00 0.20 60 61 120 pin # 1 identi fier zone 32.00 0.20 34.60 0.20 exposed heat sink appears on top surface in chip face-down version or bottom surface in chip face-up version 24 .2 ref 24. 2 ref 4.10 max
data sheet orca series 2 fpgas june 1999 182 lucent technologies inc. package outline drawings (continued) 256-pin pbga dimensions are in millimeters. 5-4406r.6 0.36 0.04 1.17 0.05 2.13 0.19 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 27.00 0.20 27.00 0.20 24.00 +0.70 C0.00 24.00 +0.70 C0.00 a1 ball identifier zone a b c d e f g h j k l m y n p r t u v w 12345678910 11 12 13 14 15 16 17 18 20 19 center array for thermal enhancement 19 spaces @ 1.27 = 24.13 a1 ball corner 19 spaces @ 1.27 = 24.13 0.75 0.15
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 183 package outline drawings (continued) 304-pin sqfp dimensions are in millimeters. 5-3307r.8 detail a detail b 4.10 max 0.50 typ seating plane 0.08 3.40 0.20 0.25 min 0.17/0.27 0.10 m 0.090/0.200 detail b 0.25 0.50/0.75 1.30 ref gage plane seating plane detail a pin #1 identifier zone 42.60 0.20 40.00 0.20 42.60 0.20 40.00 0.20 1 76 77 152 153 228 229 304
data sheet orca series 2 fpgas june 1999 184 lucent technologies inc. package outline drawings (continued) 304-pin sqfp2 dimensions are in millimeters. 5-3827(f).r8 detail a detail b 4.10 max 0.50 typ seating plane 0.08 3.40 0.20 0.25 min 0.17/0.27 0.10 m 0.090/0.200 detail b 0.25 0.50/0.75 1.30 ref gage plane seating plane detail a 42.60 0.20 40.00 0.20 42.60 0.20 40.00 0.20 1 76 77 152 153 228 229 304 pin #1 identifier zone exposed heat sink appears on top surface in chip face-down version or bottom surface in chip face-up version 31.2 ref 31.2 ref
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 185 package outline drawings (continued) 352-pin pbga dimensions are in millimeters. 5-4407r.4 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 35.00 +0.70 C0.00 30.00 a1 ball identifier zone af ae ad ac ab aa y w v u t r g 25 spaces @ 1.27 = 31.75 p n m l k j h 1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 26 20 11 13 15 17 21 19 23 25 f e d c b a center array 25 spaces a1 ball 0.75 0.15 35.00 0.20 30.00 +0.70 C0.00 0.20 @ 1.27 = 31.75 for thermal enhancement corner
data sheet orca series 2 fpgas june 1999 186 lucent technologies inc. package outline drawings (continued) 432-pin ebga dimensions are in millimeters. 5-4409r.3 0.91 0.06 1.54 0.13 seating plane solder ball 0.63 0.07 0.20 40.00 0.10 40.00 a1 ball m d ag b f k h g e ad l t j n aj c y p ah ae ac aa w u r ak af ab v al a 19 30 26 5 28 24 22 23 25 7 20 31 29 15 21 18 327 11 17 4 6 810121416 2 913 1 30 spaces @ 1.27 = 38.10 30 spaces a1 ball 0.75 0.15 identifier zone 0.10 @ 1.27 = 38.10 corner
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 187 ordering information or2c12a, -4 speed grade, 240-pin shrink quad flat pack, commercial temperature. table 56. fpga voltage options device voltage or2cxxa 5.0 v or2txxa 3.3 v or2txxb 3.3 v table 57. fpga temperature options symbol description temperature (blank) commercial 0 c to 70 c i industrial C40 c to +85 c table 58. fpga package options symbol description ba plastic ball grid array (pbga) bc enhanced ball grid array (ebga) j quad flat package (qfp) m plastic leaded chip carrier (plcc) ps power quad shrink flat package (sqfp2) s shrink quad flat package (sqfp) t thin quad flat package (tqfp) or2c12a-4 s 240 device type speed grade package type number of pins temperature range example:
data sheet orca series 2 fpgas june 1999 188 lucent technologies inc. ordering information (continued) key: c = commercial, i = industrial. key: c = commercial, i = industrial. notes: the package options with the sqfp/sqfp2 designation in the table above use the sqfp package for all densities up to and includi ng the or2c/t15a/b, while the or2c/t26a and the or2c/2t40a/b use the sqfp2. the or2txxa and or2txxb series is not offered in the 304-pin sqfp/sqfp2 packages. the or2c40a is not offered in a 352-pin pbga. table 59. orca or2cxxa/or2txxa series package matrix packages 84-pin plcc 100-pin tqfp 144-pin tqfp 160-pin qfp 208-pin eiaj sqfp/ sqfp2 240-pin eiaj sqfp/ sqfp2 256-pin pbga 304-pin eiaj sqfp/ sqfp2 352-pin pbga 432-pin ebga m84 t100 t144 j160 s208/ ps208 s240/ ps240 ba256 s304/ ps304 ba352 bc432 or2c/2t04a ci ci ci ci ci or2c/2t06a ci ci ci ci ci ci ci or2c/2t08a ci ci ci ci ci or2c/2t10a ci ci ci ci ci ci or2c/2t12acicicicicici or2c/2t15acicicicicicici or2c/2t26acicicicici or2c/2t40a cicicicici table 60. orca or2txxb series package matrix packages 84-pin plcc 100-pin tqfp 144-pin tqfp 160-pin qfp 208-pin eiaj sqfp/ sqfp2 240-pin eiaj sqfp/ sqfp2 256-pin pbga 304-pin eiaj sqfp/ sqfp2 352-pin pbga 432-pin ebga m84 t100 t144 j160 s208/ ps208 s240/ ps240 ba256 s304/ ps304 ba352 bc432 or2t15bcicicici or2t40bcicicici
189 lucent technologies inc. data sheet orca series 2 fpgas june 1999 index a absolute maximum ratings, 129 adder (see lut operating modes) architecture overview, 5 plc, 22 pic, 25 b bidirectional buffers (bidis), 14, 17, 18, 20, 22 (see also routing and slic) bit stream (see fpga configuration) bit stream error checking, 47 (see also fpga states of operation) boundary scan, 5459 c clock distribution network, 3739 selecting clock input pins, 39 clock enable (ce), 1, 5, 7, 15, 16, 24, 134 comparator (see lut operating modes) configuration (see fpga states of operation or fpga configuration) control inputs, 5, 7 e electrical characteristics, 130 error checking (see fpga configuration) f 5 v tolerant i/o, 2627, 64 fpga configuration configuration frame format, 4346 configuration modes, 47, 158160 asynchronous peripheral mode, 49, 163 daisy-chaining, 51 master parallel mode, 47 master serial mode, 162 slave parallel mode, 48, 50, 161, 166 slave serial mode, 4950, 165 synchronous peripheral mode, 48, 164 data format, 4345 using orca foundry to generate ram data, 43 fpga states of operation, 4043 configuration, 41 initialization, 40 other configuration options, 43 partial reconfiguration, 43 reconfiguration, 42 start-up, 41 g gsr (see gsrn) gsrn, 6, 7, 16, 37, 134 i ieee standard 1149.1, 1 (see also boundary scan) initialization (see fpga states of operation) input/output buffers (see pics) measurement conditions, 169 output buffer characteristics, 170172 j jtag (see boundary scan) l look-up table (lut) operating modes, 715 adder-subtractor submode, 10 counter submode, 11 equality comparators, 11 logic modes, 79 memory mode, 1215 asynchronous memory, 12 synchronous memory, 13 multiplier submode, 11 ripple mode, 10 lsr, 57, 1516 m maximum ratings (see absolute maximum ratings) multiplier (see lut operating modes) o orca foundry development system overview, 4 ordering information, 189 package matrix, 190 package options, 189 temperature options, 189 voltage options, 189 output (see pics) p package outline drawings, 174186 package matrix, 190 package outline drawings, 173 84-pin plcc, 174 100-pin tqfp, 175 144-pin tqfp, 176
lucent technologies inc. 190 data sheet june 1999 orca series 2 fpgas index (continued) 160-pin qfp, 177 208-pin sqfp, 178 208-pin sqfp2, 179 240-pin sqfp, 180 240-pin sqfp2, 181 256-pin pbga, 182 304-pin sqfp, 183 304-pin sqfp2, 184 352-pin pbga, 185 432-pin ebga, 186 terms and definitions, 173 pin information, 71125 84-pin plcc, 71 100-pin tqfp, 73 144-pin tqfp, 75 160-pin qfp, 77 208-pin sqfp/sqfp2, 81 240-pin sqfp/sqfp2, 86 256-pin pbga, 92 304-pin sqfp/sqfp2, 99 352-pin pbga, 106 432-pin ebga pinout, 116 package compatibility, 6870 pin descriptions, 71 power dissipation, 6165 5 v tolerant i/o, 64 or2cxxa, 61 or2txxa, 63 programmable function unit (pfu), 516 control inputs, 5, 7 operating modes, 715 latches/flip-flops, 1516 programmable input/output cells (pics), 2531 5 v tolerant i/o, 26 architecture, 2930 inputs, 25 outputs, 26 open-drain output option, 26 propagation delays, 26 overview, 25 zero-hold input, 25 programmable logic cells (plcs), 524 architecture, 2224 latches/flip-flops, 1516 pfu, 516 routing, 1724 r ram (see also fpga configuration), 17, 44, 135, 142 dual-port, 3, 7, 1315 single-port, 3, 7, 1215 recommended operating conditions, 129 reconfiguration (see fpga states of operation) routing 3-statable bidirectional buffers, 1718, 148 clock routing, 24, 149153 (see also clock distribution network) configurable interconnect points (cips), 17 fast-carry routing, 24 inter-plc routing resources, 1819 interquad routing, 5, 17, 3236 intra-plc routing resources, 18 minimizing routing delay, 20 plc routing, 1724, 34 programmable corner cell routing, 37 pic routing, 2731 s boundary scan, 54C59 global 3-state control (ts_all), 37, 66 global set/reset (gsrn), 7, 16, 37 internal oscillator, 37 readback logic, 37 start-up, 41 (see also fpga states of operation) subtractor (see lut operating modes) system clock (see clock distribution network) t 3-state (see bidirectional buffers, ts_all) timing characteristics, 132C168 asynchronous peripheral configuration mode, 163 boundary-scan timing, 168 clock timing, 149 general configuration mode timing, 158 master parallel configuration mode, 162 master serial configuration mode, 161 pfu timing, 132 pio timing, 154 plc timing, 148 readback timing, 167 slave parallel configuration mode, 166 slave serial configuration mode, 165 tolerant i/o, 26 (see also 5 v tolerant i/o) ts_all, 1, 37, 66 uz zero-hold inputs, 25
data sheet june 1999 orca series 2 fpgas lucent technologies inc. 191 notes
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. foundry is a trademark of xilinx inc. copyright ? 1999 lucent technologies inc. all rights reserved june 1999 ds99-094fpga (replaces ds98-022fpga) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

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